犬石 昌秀

教授(任期付)

  • 809 引用
  • 15 h指数
1976 …2019

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

  • 809 引用
  • 15 h指数
  • 41 Article
  • 39 Conference article
  • 13 Conference contribution
  • 8 Paper
2019

Backside layout design of Snapback-free RCIGBT with multiple-cell

Chang, Z., Zhu, X. & Inuishi, M., 2019 1 1, : : Lecture Notes in Engineering and Computer Science. 2239, p. 299-303 5 p.

研究成果: Conference article

2016

On the scaling limit of the Si-IGBTs with very narrow mesa structure

Eikyu, K., Sakai, A., Matsuura, H., Nakazawa, Y., Akiyama, Y., Yamaguchi, Y. & Inuishi, M., 2016 7 25, Proceedings of the 2016 28th International Symposium on Power Semiconductor Devices and ICs, ISPSD 2016. Institute of Electrical and Electronics Engineers Inc., 巻 2016-July. p. 211-214 4 p. 7520815

研究成果: Conference contribution

24 引用 (Scopus)
2011

Study of current induced magnetic domain wall movement with extremely low energy consumption by micromagnetic simulation

Kawabata, K., Tanizawa, M., Ishikawa, K., Inoue, Y., Inuishi, M. & Nishimura, T., 2011 11 1, 2011 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2011. p. 55-58 4 p. 6035048. (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD).

研究成果: Conference contribution

2 引用 (Scopus)
2007

A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

Ohbayashi, S., Yabuuchi, M., Nil, K., Tsukamoto, Y., Imaoka, S., Oda, Y., Yoshihara, T., Igarashi, M., Takeuchi, M., Kawashima, H., Yamaguchi, Y., Tsukamoto, K., Inuishi, M., Makino, H., Ishibashi, K. & Shinohara, H., 2007 4 1, : : IEEE Journal of Solid-State Circuits. 42, 4, p. 820-829 10 p.

研究成果: Article

86 引用 (Scopus)
2006

A 65 nm SoC embedded 6T-SRAM design for manufacturing with read and write cell stabilizing circuits

Ohbayashi, S., Yabuuchi, M., Nii, K., Tsukamoto, Y., Imaoka, S., Oda, Y., Igarashi, M., Takeuchi, M., Kawashima, H., Makino, H., Yamaguchi, Y., Tsukamoto, K., Inuishi, M., Ishibashi, K. & Shinohara, H., 2006 12 1, 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. p. 17-18 2 p. 1705290. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

41 引用 (Scopus)
2005

A novel mobility-variation-free extraction technique of capacitance coupling coefficient for stacked flash memory cell

Okagaki, T., Tanizawa, M., Fujinaga, M., Kunikiyo, T., Yuki, H., Ishikawa, K., Nishikawa, Y., Eimori, T., Inuishi, M. & Oji, Y., 2005 11 15, p. 219-222. 4 p.

研究成果: Paper

Novel shallow trench isolation process from viewpoint of total strain process design for 45 nm node devices and beyond

Ishibashi, M., Horita, K., Sawada, M., Kitazawa, M., Igarashi, M., Kuroi, T., Eimori, T., Kobayashi, K., Inuishi, M. & Ohji, Y., 2005 4 1, : : Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 44, 4 B, p. 2152-2156 5 p.

研究成果: Article

12 引用 (Scopus)
2004

Body bias controlled SOI technology with HTI

Tsujiuchi, M., Hirano, Y., Iwamatsu, T., Ipposhi, T., Maegawa, S., Inuishi, M. & Ohji, Y., 2004, IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai. Institute of Electrical and Electronics Engineers Inc., p. 131-132 2 p. 1566443

研究成果: Conference contribution

Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond

Yamashita, T., Shiga, K., Hayashi, T., Umeda, H., Oda, H., Eimori, T., Inuishi, M., Ohji, Y., Eriguchi, K., Nakanishi, K., Nakaoka, H., Yamada, T., Nakamura, M., Miyanaga, I., Kajiya, A., Kubota, M. & Ogura, M., 2004, IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai. Institute of Electrical and Electronics Engineers Inc., p. 123-124 2 p. 1566439

研究成果: Conference contribution

Impact of boron penetration from S/D-extension on gate-Oxide reliability for 65-nm node CMOS and beyond

Yamashita, T., Ota, K., Shiga, K., Hayashi, T., Umeda, H., Oda, H., Eimori, T., Inuishi, M., Ohji, Y., Eriguchi, K., Nakanishi, K., Nakaoka, H., Yamada, T., Nakamura, M., Miyanaga, I., Kajiya, A., Kubota, M. & Ogura, M., 2004, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 136-137 2 p.

研究成果: Conference article

6 引用 (Scopus)

Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure

Hirano, Y., Ipposhi, T., Thai, D. H., Iwamatsu, T., Ikeda, T., Tsujiuchi, M., Maegawa, S., Inuishi, M. & Ohji, Y., 2004, p. 60-64. 5 p.

研究成果: Paper

1 引用 (Scopus)
13 引用 (Scopus)
2003

An artificial fingerprint device (AFD): A study of identification number applications utilizing characteristics variation of polycrystalline silicon TFTs

Maeda, S., Kuriyama, H., Ipposhi, T., Maegawa, S., Inoue, Y., Inuishi, M., Kotani, N. & Nishimura, T., 2003 6 1, : : IEEE Transactions on Electron Devices. 50, 6, p. 1451-1458 8 p.

研究成果: Article

21 引用 (Scopus)

Impact of Actively Body-bias Controlled (ABC) SOI SRAM by using Direct Body Contact Technology for Low-Voltage Application

Hirano, Y., Ipposhi, T., Dang, H., Matsumoto, T., Iwamatsu, T., Nii, K., Tsukamoto, Y., Yoshizawa, T., Kato, H., Maegawa, S., Arimoto, K., Inoue, Y., Inuishi, M. & Ohji, Y., 2003 12 1, : : Technical Digest - International Electron Devices Meeting. p. 35-38 4 p.

研究成果: Conference article

9 引用 (Scopus)
2002
12 引用 (Scopus)

Clarification of floating-body effects on drive current and short channel effect in deep sub-0.25 μm partially depleted SOI MOSFETs

Matsumoto, T., Maeda, S., Hirano, Y., Eikyu, K., Yamaguchi, Y., Maegawa, S., Inuishi, M. & Nishimura, T., 2002 1 1, : : IEEE Transactions on Electron Devices. 49, 1, p. 55-60 6 p.

研究成果: Article

5 引用 (Scopus)

Sub-1 μm2 high density embedded SRAM technologies for 100 nm generation SOC and beyond

Tomita, K., Hashimoto, K., Inbe, T., Oashi, T., Tsukamoto, K., Nishioka, Y., Matsuura, M., Eimori, T., Inuishi, M., Miyanaga, I., Nakamura, M., Kishimoto, T., Yamada, T., Eriguchi, K., Yuasa, H., Satake, T., Kajiya, A. & Ogura, M., 2002 1 1, p. 14-15. 2 p.

研究成果: Paper

9 引用 (Scopus)
2001

70 nm SOI-CMOS of 135 GHz fmax with dual offset-implanted source-drain extension structure for RF/analog and logic applications

Matsumoto, T., Maeda, S., Ota, K., Hirano, Y., Eikyu, K., Sayama, H., Iwamatsu, T., Yamamoto, K., Katoh, T., Yamaguchi, Y., Ipposhi, T., Oda, H., Maegawa, S., Inoue, Y. & Inuishi, M., 2001 12 1, : : Technical Digest - International Electron Devices Meeting. p. 219-222 4 p.

研究成果: Conference article

21 引用 (Scopus)
4 引用 (Scopus)

Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI)

Hirano, Y., Maeda, S., Matsumoto, T., Nii, K., Iwamatsu, T., Yamaguchi, Y., Ipposhi, T., Kawashima, H., Maegawa, S., Inuishi, M. & Nishimura, T., 2001 12 1, : : IEEE Transactions on Electron Devices. 48, 12, p. 2816-2822 7 p.

研究成果: Article

8 引用 (Scopus)

Evaluation of soft errors in DRAM and SRAM using nuclear microprobe and neutron source

Takai, M., Arita, Y., Abo, S., Iwamatsu, T., Maegawa, S., Sayama, H., Yamaguchi, Y., Inuishi, M. & Nishimura, T., 2001 1 1, European Solid-State Device Research Conference. Ryssel, H., Wachutka, G. & Grunbacher, H. (版). IEEE Computer Society, p. 17-24 8 p. (European Solid-State Device Research Conference).

研究成果: Conference contribution

Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

Maeda, S., Wada, Y., Yamamoto, K., Komurasaki, H., Matsumoto, T., Hirano, Y., Iwamatsu, T., Yamaguchi, Y., Ipposhi, T., Ueda, K., Mashiko, K., Maegawa, S. & Inuishi, M., 2001 9 1, : : IEEE Transactions on Electron Devices. 48, 9, p. 2065-2073 9 p.

研究成果: Article

17 引用 (Scopus)

SoC CMOS technology for NBTI/HCI immune I/O and analog circuits implementing surface and buried channel structures

Nishida, Y., Sayama, H., Ohta, K., Oda, H., Katayama, M., Inoue, Y., Morimoto, H. & Inuishi, M., 2001 12 1, : : Technical Digest - International Electron Devices Meeting. p. 869-872 4 p.

研究成果: Conference article

5 引用 (Scopus)
2000

80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

Sayama, H., Nishida, Y., Oda, H., Tsuchimoto, J., Umeda, H., Teramoto, A., Eikyu, K., Inoue, Y. & Inuishi, M., 2000 12 1, : : Technical Digest - International Electron Devices Meeting. p. 239-242 4 p.

研究成果: Conference article

11 引用 (Scopus)

Advanced shallow trench isolation to suppress the inverse narrow channel effects for 0.24 μm pitch isolation and beyond

Horita, K., Kuroi, T., Itoh, Y., Shiozawa, K., Eikyu, K., Goto, K., Inoue, Y. & Inuishi, M., 2000 1 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 178-179 2 p.

研究成果: Conference article

16 引用 (Scopus)

Direct measurement of transient drain currents in partially-depleted SOI N-channel MOSFETs using a nuclear microprobe for highly reliable device designs

Iwamatsu, T., Nakayama, K., Takaoka, H., Takai, M., Yamaguchi, Y., Maegawa, S., Inuishi, M., Kinomura, A., Horino, Y. & Nlshimura, T., 2000, : : Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 39, 4 B, p. 2236-2240 5 p.

研究成果: Article

9 引用 (Scopus)

Extraction of the physical oxide thickness using the electrical characteristics of MOS capacitors

Eikyu, K., Takashino, H., Kidera, M., Teramoto, A., Umeda, H., Ishikawa, K., Kotani, N. & Inuishi, M., 2000 1 1, p. 257-260. 4 p.

研究成果: Paper

1 引用 (Scopus)

High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization

Takenaka, N., Segawa, M., Uehara, T., Akamatsu, S., Matsumoto, M., Kurimoto, K., Ueda, T., Watanabe, H., Matsutani, T., Yoneda, K., Koshio, A., Kato, Y., Inuishi, M., Oashi, T. & Tsukamoto, K., 2000 1 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 62-63 2 p.

研究成果: Conference article

10 引用 (Scopus)

Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

Hirano, Y., Matsumoto, T., Maeda, S., Iwamatsu, T., Kunikiyo, T., Nii, K., Yamamoto, K., Yamaguchi, Y., Ipposhi, T., Maegawa, S. & Inuishi, M., 2000 12 1, : : Technical Digest - International Electron Devices Meeting. p. 467-470 4 p.

研究成果: Conference article

27 引用 (Scopus)

Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

Maeda, S., Wada, Y., Yamamoto, K., Komurasaki, H., Matsumoto, T., Hirano, Y., Iwamatsu, T., Yamaguchi, Y., Ipposhi, T., Ueda, K., Mashiko, K., Maegawa, S. & Inuishi, M., 2000 1 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 154-155 2 p.

研究成果: Conference article

12 引用 (Scopus)
3 引用 (Scopus)

New cell technology for the scalable BST capacitor using damascene-formed pedestal electrode with a [Pt-Ir] alloy coating

Itoh, H., Tsunemine, Y., Yutani, A., Okudaira, T., Kashihara, K., Inuishi, M., Yamamuka, M., Kawahara, T., Horikawa, T., Ohmori, T. & Satoh, S., 2000 1 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 106-107 2 p.

研究成果: Conference article

4 引用 (Scopus)
9 引用 (Scopus)

Suppression of stress induced drain leakage current of SOI MOSFETs by using partial trench isolation technology

Iwamatsu, T., Ipposhi, T., Uchida, T., Maegawa, S. & Inuishi, M., 2000 12 1, p. 80-81. 2 p.

研究成果: Paper

4 引用 (Scopus)
1999

Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI)

Hirano, Y., Maeda, S., Matsumoto, T., Nii, K., Iwamatsu, T., Yamaguchi, Y., Ipposhi, T., Kawashima, H., Maegawa, S., Inuishi, M. & Nishimura, T., 1999 1 1, 1999 IEEE International SOI Conference, SOI 1999 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 131-132 2 p. 819887. (1999 IEEE International SOI Conference, SOI 1999 - Proceedings).

研究成果: Conference contribution

Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI)

Hirano, Y., Maeda, S., Matsumoto, T., Nii, K., Iwamatsu, T., Yamaguchi, Y., Ipposhi, T., Kawashima, H., Maegawa, S., Inuishi, M. & Nishimura, T., 1999 12 1, p. 131-132. 2 p.

研究成果: Paper

4 引用 (Scopus)

Effect of 〈100〉 channel direction for high performance SCE immune pMOSFET with less than 0.15μm gate length

Sayama, H., Nishida, Y., Oda, H., Oishi, T., Shimizu, S., Kunikiyo, T., Sonoda, K., Inoue, Y. & Inuishi, M., 1999 12 1, : : Technical Digest - International Electron Devices Meeting. p. 657-660 4 p.

研究成果: Conference article

33 引用 (Scopus)
18 引用 (Scopus)
1998

Approaches to extra low voltage dram operation by soi-dram

Eimori, T., Oashi, T., Morishita, F., Iwamatsu, T., Yamaguchi, Y., Okuda, F., Shimomura, K. N. I., Shimano, H., Sakashita, N., Arimoto, K., Inoue, Y., Komori, S., Inuishi, M., Nishimura, T. & Miyoshi, H., 1998 12 1, : : IEEE Transactions on Electron Devices. 45, 5, p. 1000-1009 10 p.

研究成果: Article

15 引用 (Scopus)
1997

1 V 46 ns 16 Mb SOI-DRAM with body control technique

Shimomura, K., Shimano, H., Okuda, F., Sakashita, N., Yamaguchi, Y., Oashi, T., Eimori, T., Inuishi, M., Arimoto, K., Maegawa, S., Inoue, Y., Nishimura, T., Komori, S., Kyuma, K., Yasuoka, A. & Abe, H., 1997 2 1, : : Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 40, p. 68-69 2 p.

研究成果: Conference article

14 引用 (Scopus)

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

Shimomura, K., Shimano, H., Sakashita, N., Okuda, F., Oashi, T., Yamaguchi, Y., Eimori, T., Inuishi, M., Arimoto, K., Maegawa, S., Inoue, Y., Komori, S. & Kyuma, K., 1997 11, : : IEEE Journal of Solid-State Circuits. 32, 11, p. 1712-1718 7 p.

研究成果: Article

6 引用 (Scopus)

Application of nitrogen implantation to ULSI

Murakami, T., Kuroi, T., Kawasaki, Y., Inuishi, M., Matsui, Y. & Yasuoka, A., 1997 1, : : Nuclear Instruments and Methods in Physics Research, Section B: Beam Interactions with Materials and Atoms. 121, 1-4, p. 257-261 5 p.

研究成果: Article

25 引用 (Scopus)
4 引用 (Scopus)

Gate electrode engineering by control of grain growth for high performance and high reliable 0.18 μm dual gate CMOS

Shimizu, S., Kuroi, T., Sayama, H., Furukawa, A., Nishida, Y., Inoue, Y., Inuishi, M. & Nishimura, T., 1997 1 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 107-108 2 p.

研究成果: Conference article

10 引用 (Scopus)

Merged logic and DRAM

Inuishi, M., Havemann, B., Yamawaki, M., Stiffler, S., Kim, C., Lu, N., Scott, D., Tomisawa, O., Ishiuchi, H., Choi, C. S., Kalter, H., Pollack, F. & Puar, D., 1997, : : Digest of Technical Papers - Symposium on VLSI Technology. 1 p.

研究成果: Conference article