犬石 昌秀

教授(任期付)

  • 808 引用
  • 15 h指数
1976 …2019

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

  • 808 引用
  • 15 h指数
  • 41 Article
  • 39 Conference article
  • 13 Conference contribution
  • 8 Paper
フィルター
Conference contribution
2016

On the scaling limit of the Si-IGBTs with very narrow mesa structure

Eikyu, K., Sakai, A., Matsuura, H., Nakazawa, Y., Akiyama, Y., Yamaguchi, Y. & Inuishi, M., 2016 7 25, Proceedings of the 2016 28th International Symposium on Power Semiconductor Devices and ICs, ISPSD 2016. Institute of Electrical and Electronics Engineers Inc., 巻 2016-July. p. 211-214 4 p. 7520815

研究成果: Conference contribution

24 引用 (Scopus)
2011

Study of current induced magnetic domain wall movement with extremely low energy consumption by micromagnetic simulation

Kawabata, K., Tanizawa, M., Ishikawa, K., Inoue, Y., Inuishi, M. & Nishimura, T., 2011 11 1, 2011 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2011. p. 55-58 4 p. 6035048. (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD).

研究成果: Conference contribution

2 引用 (Scopus)
2006

A 65 nm SoC embedded 6T-SRAM design for manufacturing with read and write cell stabilizing circuits

Ohbayashi, S., Yabuuchi, M., Nii, K., Tsukamoto, Y., Imaoka, S., Oda, Y., Igarashi, M., Takeuchi, M., Kawashima, H., Makino, H., Yamaguchi, Y., Tsukamoto, K., Inuishi, M., Ishibashi, K. & Shinohara, H., 2006 12 1, 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. p. 17-18 2 p. 1705290. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

41 引用 (Scopus)
2004

Body bias controlled SOI technology with HTI

Tsujiuchi, M., Hirano, Y., Iwamatsu, T., Ipposhi, T., Maegawa, S., Inuishi, M. & Ohji, Y., 2004, IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai. Institute of Electrical and Electronics Engineers Inc., p. 131-132 2 p. 1566443

研究成果: Conference contribution

Impact of boron penetration from S/D-extension on gate leakage current and gate-oxide reliability for 65-nm node CMOS and beyond

Yamashita, T., Shiga, K., Hayashi, T., Umeda, H., Oda, H., Eimori, T., Inuishi, M., Ohji, Y., Eriguchi, K., Nakanishi, K., Nakaoka, H., Yamada, T., Nakamura, M., Miyanaga, I., Kajiya, A., Kubota, M. & Ogura, M., 2004, IMFEDK 2004 - International Meeting for Future of Electron Devices, Kansai. Institute of Electrical and Electronics Engineers Inc., p. 123-124 2 p. 1566439

研究成果: Conference contribution

2001

Evaluation of soft errors in DRAM and SRAM using nuclear microprobe and neutron source

Takai, M., Arita, Y., Abo, S., Iwamatsu, T., Maegawa, S., Sayama, H., Yamaguchi, Y., Inuishi, M. & Nishimura, T., 2001 1 1, European Solid-State Device Research Conference. Ryssel, H., Wachutka, G. & Grunbacher, H. (版). IEEE Computer Society, p. 17-24 8 p. (European Solid-State Device Research Conference).

研究成果: Conference contribution

1999

Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI)

Hirano, Y., Maeda, S., Matsumoto, T., Nii, K., Iwamatsu, T., Yamaguchi, Y., Ipposhi, T., Kawashima, H., Maegawa, S., Inuishi, M. & Nishimura, T., 1999 1 1, 1999 IEEE International SOI Conference, SOI 1999 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 131-132 2 p. 819887. (1999 IEEE International SOI Conference, SOI 1999 - Proceedings).

研究成果: Conference contribution

1993

Novel NICE (Nitrogen implantation into CMOS gate electrode and source-drain) structure for high reliability and high performance 0. 25μm dual gate CMOS

Kuroi, T., Yamaguchi, T., Shirahata, M., Okumura, Y., Kawasaki, Y., Inuishi, M. & Tsubouchi, B., 1993 12 1, Technical Digest - International Electron Devices Meeting. Anon (版). Publ by IEEE, p. 324-328 5 p. (Technical Digest - International Electron Devices Meeting).

研究成果: Conference contribution

8 引用 (Scopus)
1991

Gate capacitance characteristics of gate N/sup -/ overlap LDD transistor with high performance and high reliability

Inuishi, M., Mitsui, K., Kusunoki, S., Oda, H., Tsukamoto, K. & Akasaka, Y., 1991, International Electron Devices Meeting 1991, IEDM 1991. Institute of Electrical and Electronics Engineers Inc., 巻 1991-January. p. 371-374 4 p. 235376

研究成果: Conference contribution

10 引用 (Scopus)

Hot-carrier-resistant structure by Re-oxidized nitrided oxide sidewall for highly reliable and high performance LDD MOSFETs

Kusunoki, S., Inuishi, M., Yamaguchi, T., Tsukamoto, K. & Akasaka, Y., 1991, International Electron Devices Meeting 1991, IEDM 1991. Institute of Electrical and Electronics Engineers Inc., 巻 1991-January. p. 649-652 4 p. 235388

研究成果: Conference contribution

2 引用 (Scopus)
1989

A highly reliable gate/n- overlapped transistor for mega-bit DRAMs

Nagatomo, M., Okumura, Y., Mitsui, K., Ogoh, I., Genjoh, H., Inuishi, M. & Matsukawa, T., 1989 1 1, ESSDERC 1989 - Proceedings of the 19th European Solid State Device Research Conference. Heuberger, A., Ryssel, H. & Lange, P. (版). IEEE Computer Society, p. 923-926 4 p. 5437066. (European Solid-State Device Research Conference).

研究成果: Conference contribution

2 引用 (Scopus)
1987

MeV-BORON IMPLANTED BURIED BARRIER FOR SOFT ERROR REDUCTION IN MEGABIT DRAM.

Matsuda, Y., Tsukamoto, K., Inuishi, M., Shimizu, M., Asakura, M., Fujishima, K., Komori, J. & Akasaka, Y., 1987, Conference on Solid State Devices and Materials. Japan Soc of Applied Physics, p. 23-26 4 p. (Conference on Solid State Devices and Materials).

研究成果: Conference contribution

7 引用 (Scopus)
1985

SUBMICRON LITHOGRAPHY USING FOCUSED-ION-BEAM EXPOSURE FOLLOWED BY A DRY DEVELOPMENT.

Kato, T., Morimoto, H., Tsukamoto, K., Shinohara, H. & Inuishi, M., 1985 12 1, Digest of Technical Papers - Symposium on VLSI Technology. Business Cent for Academic Soc Japan, p. 72-73 2 p. (Digest of Technical Papers - Symposium on VLSI Technology).

研究成果: Conference contribution