犬石 昌秀

教授(任期付)

  • 809 引用
  • 15 h指数
1976 …2019

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

  • 809 引用
  • 15 h指数
  • 41 Article
  • 39 Conference article
  • 13 Conference contribution
  • 8 Paper
フィルター
Conference article
2019

Backside layout design of Snapback-free RCIGBT with multiple-cell

Chang, Z., Zhu, X. & Inuishi, M., 2019 1 1, : : Lecture Notes in Engineering and Computer Science. 2239, p. 299-303 5 p.

研究成果: Conference article

2004

Impact of boron penetration from S/D-extension on gate-Oxide reliability for 65-nm node CMOS and beyond

Yamashita, T., Ota, K., Shiga, K., Hayashi, T., Umeda, H., Oda, H., Eimori, T., Inuishi, M., Ohji, Y., Eriguchi, K., Nakanishi, K., Nakaoka, H., Yamada, T., Nakamura, M., Miyanaga, I., Kajiya, A., Kubota, M. & Ogura, M., 2004, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 136-137 2 p.

研究成果: Conference article

6 引用 (Scopus)
2003

Impact of Actively Body-bias Controlled (ABC) SOI SRAM by using Direct Body Contact Technology for Low-Voltage Application

Hirano, Y., Ipposhi, T., Dang, H., Matsumoto, T., Iwamatsu, T., Nii, K., Tsukamoto, Y., Yoshizawa, T., Kato, H., Maegawa, S., Arimoto, K., Inoue, Y., Inuishi, M. & Ohji, Y., 2003 12 1, : : Technical Digest - International Electron Devices Meeting. p. 35-38 4 p.

研究成果: Conference article

9 引用 (Scopus)
2001

70 nm SOI-CMOS of 135 GHz fmax with dual offset-implanted source-drain extension structure for RF/analog and logic applications

Matsumoto, T., Maeda, S., Ota, K., Hirano, Y., Eikyu, K., Sayama, H., Iwamatsu, T., Yamamoto, K., Katoh, T., Yamaguchi, Y., Ipposhi, T., Oda, H., Maegawa, S., Inoue, Y. & Inuishi, M., 2001 12 1, : : Technical Digest - International Electron Devices Meeting. p. 219-222 4 p.

研究成果: Conference article

21 引用 (Scopus)
4 引用 (Scopus)

SoC CMOS technology for NBTI/HCI immune I/O and analog circuits implementing surface and buried channel structures

Nishida, Y., Sayama, H., Ohta, K., Oda, H., Katayama, M., Inoue, Y., Morimoto, H. & Inuishi, M., 2001 12 1, : : Technical Digest - International Electron Devices Meeting. p. 869-872 4 p.

研究成果: Conference article

5 引用 (Scopus)
2000

80nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

Sayama, H., Nishida, Y., Oda, H., Tsuchimoto, J., Umeda, H., Teramoto, A., Eikyu, K., Inoue, Y. & Inuishi, M., 2000 12 1, : : Technical Digest - International Electron Devices Meeting. p. 239-242 4 p.

研究成果: Conference article

11 引用 (Scopus)

Advanced shallow trench isolation to suppress the inverse narrow channel effects for 0.24 μm pitch isolation and beyond

Horita, K., Kuroi, T., Itoh, Y., Shiozawa, K., Eikyu, K., Goto, K., Inoue, Y. & Inuishi, M., 2000 1 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 178-179 2 p.

研究成果: Conference article

16 引用 (Scopus)

High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization

Takenaka, N., Segawa, M., Uehara, T., Akamatsu, S., Matsumoto, M., Kurimoto, K., Ueda, T., Watanabe, H., Matsutani, T., Yoneda, K., Koshio, A., Kato, Y., Inuishi, M., Oashi, T. & Tsukamoto, K., 2000 1 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 62-63 2 p.

研究成果: Conference article

10 引用 (Scopus)

Impact of 0.10 μm SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

Hirano, Y., Matsumoto, T., Maeda, S., Iwamatsu, T., Kunikiyo, T., Nii, K., Yamamoto, K., Yamaguchi, Y., Ipposhi, T., Maegawa, S. & Inuishi, M., 2000 12 1, : : Technical Digest - International Electron Devices Meeting. p. 467-470 4 p.

研究成果: Conference article

27 引用 (Scopus)

Impact of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

Maeda, S., Wada, Y., Yamamoto, K., Komurasaki, H., Matsumoto, T., Hirano, Y., Iwamatsu, T., Yamaguchi, Y., Ipposhi, T., Ueda, K., Mashiko, K., Maegawa, S. & Inuishi, M., 2000 1 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 154-155 2 p.

研究成果: Conference article

12 引用 (Scopus)

New cell technology for the scalable BST capacitor using damascene-formed pedestal electrode with a [Pt-Ir] alloy coating

Itoh, H., Tsunemine, Y., Yutani, A., Okudaira, T., Kashihara, K., Inuishi, M., Yamamuka, M., Kawahara, T., Horikawa, T., Ohmori, T. & Satoh, S., 2000 1 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 106-107 2 p.

研究成果: Conference article

4 引用 (Scopus)
9 引用 (Scopus)
1999

Effect of 〈100〉 channel direction for high performance SCE immune pMOSFET with less than 0.15μm gate length

Sayama, H., Nishida, Y., Oda, H., Oishi, T., Shimizu, S., Kunikiyo, T., Sonoda, K., Inoue, Y. & Inuishi, M., 1999 12 1, : : Technical Digest - International Electron Devices Meeting. p. 657-660 4 p.

研究成果: Conference article

33 引用 (Scopus)
18 引用 (Scopus)
1997

1 V 46 ns 16 Mb SOI-DRAM with body control technique

Shimomura, K., Shimano, H., Okuda, F., Sakashita, N., Yamaguchi, Y., Oashi, T., Eimori, T., Inuishi, M., Arimoto, K., Maegawa, S., Inoue, Y., Nishimura, T., Komori, S., Kyuma, K., Yasuoka, A. & Abe, H., 1997 2 1, : : Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 40, p. 68-69 2 p.

研究成果: Conference article

14 引用 (Scopus)

Gate electrode engineering by control of grain growth for high performance and high reliable 0.18 μm dual gate CMOS

Shimizu, S., Kuroi, T., Sayama, H., Furukawa, A., Nishida, Y., Inoue, Y., Inuishi, M. & Nishimura, T., 1997 1 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 107-108 2 p.

研究成果: Conference article

10 引用 (Scopus)

Merged logic and DRAM

Inuishi, M., Havemann, B., Yamawaki, M., Stiffler, S., Kim, C., Lu, N., Scott, D., Tomisawa, O., Ishiuchi, H., Choi, C. S., Kalter, H., Pollack, F. & Puar, D., 1997, : : Digest of Technical Papers - Symposium on VLSI Technology. 1 p.

研究成果: Conference article

1996

16Mb DRAM/SOI technologies for sub-1V operation

Oashi, T., Eimori, T., Morishita, F., Iwamatsu, T., Yamaguchi, Y., Okuda, F., Shimomura, K., Shimano, H., Sakashita, N., Arimoto, K., Inoue, Y., Komori, S., Inuishi, M., Nishimura, T. & Miyoshi, H., 1996 12 1, : : Technical Digest - International Electron Devices Meeting. p. 609-612 4 p.

研究成果: Conference article

6 引用 (Scopus)

Advanced ion implantation and rapid thermal annealing technologies for highly reliable 0.25μm dual gate CMOS

Shimizu, S., Kuroi, T., Kawasaki, Y., Tsutsumi, T., Oda, H., Inuishi, M. & Miyoshi, H., 1996 1 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 64-65 2 p.

研究成果: Conference article

2 引用 (Scopus)

Channel engineering in sub-quarter-micron MOSFETs using nitrogen implantation for low voltage operation

Furukawa, A., Abe, Y., Shimizu, S., Kuroi, T., Tokuda, Y. & Inuishi, M., 1996 1 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 62-63 2 p.

研究成果: Conference article

8 引用 (Scopus)

Impact of high pressure dry O2 oxidation on sub-quarter micron planarized LOCOS

Yamashita, T., Kuroi, T., Uchida, T., Komori, S., Kobayashi, K., Inuishi, M. & Miyoshi, H., 1996 12 1, : : Technical Digest - International Electron Devices Meeting. p. 821-824 4 p.

研究成果: Conference article

1 引用 (Scopus)

Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel

Sayama, H., Kuroi, T., Shimizu, S., Shirahata, M., Okumura, Y., Inuishi, M. & Miyoshi, H., 1996 12 1, : : Technical Digest - International Electron Devices Meeting. p. 583-586 4 p.

研究成果: Conference article

3 引用 (Scopus)
1 引用 (Scopus)

Sub-quarter-micron dual gate CMOSFETs with ultra-thin gate oxide of 2nm

Kuroi, T., Shimizu, S., Ogino, S., Teramoto, A., Shirahata, M., Okumura, Y., Inuishi, M. & Miyoshi, H., 1996 1 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 210-211 2 p.

研究成果: Conference article

11 引用 (Scopus)
1995

Highly reliable 0.15 μm MOSFETs with surface proximity gettering (SPG) and nitrided oxide spacer using nitrogen implantation

Kuroi, T., Shimizu, S., Furukawa, A., Komori, S., Kawasaki, Y., Kusunoki, S., Okumura, Y., Inuishi, M., Tsubouchi, N. & Horie, K., 1995 12 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 19-20 2 p.

研究成果: Conference article

13 引用 (Scopus)

Impact of surface proximity gettering and nitrided oxide side-wall spacer by nitrogen implantation on sub-quarter micron CMOS LDD FETs

Shimizu, S., Kuroi, T., Kawasaki, Y., Kusunoki, S., Okumura, Y., Inuishi, M. & Miyoshi, H., 1995 12 1, : : Technical Digest - International Electron Devices Meeting. p. 859-862 4 p.

研究成果: Conference article

12 引用 (Scopus)
1994

0.15 μm CMOS process for high performance and high reliability

Shimizu, S., Kuroi, T., Kobayashi, M., Yamaguchi, T., Fujino, T., Maeda, H., Tsutsumi, T., Hirose, Y., Kusunoki, S., Inuishi, M. & Tsubouchi, N., 1994 12 1, : : Technical Digest - International Electron Devices Meeting. p. 67-70 4 p.

研究成果: Conference article

12 引用 (Scopus)

Effects of nitrogen implantation into P+ poly-silicon gate on gate oxide properties

Kuroi, T., Kusunoki, S., Shirahata, M., Okumura, Y., Kobayashi, M., Inuishi, M. & Tsubouchi, N., 1994 12 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 107-108 2 p.

研究成果: Conference article

23 引用 (Scopus)
1 引用 (Scopus)

Novel double well with buffer N- and P+ gettering layers for suppression of soft error rate (DOWNSER)

Komori, S., Yamashita, T., Kuroi, T., Inuishi, M. & Tsubouchi, N., 1994 12 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 41-42 2 p.

研究成果: Conference article

1 引用 (Scopus)
1991

Scalability and operating voltage of gate/N- overlap LDD in sub-half-micron regime

Shimizu, M., Inuishi, M., Tsukamoto, K. & Akasaka, Y., 1991 12 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 47-48 2 p.

研究成果: Conference article

1989
8 引用 (Scopus)

New process technology for a 4 Mbit SRAM with polysilicon load resistor cell

Yuzuriha, K., Ichinose, K., Mukai, T., Kohno, Y., Shimizu, M., Inuishi, M. & Matsukawa, T., 1989 12 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 61-62 2 p.

研究成果: Conference article

1 引用 (Scopus)

Optimum design of gate/N- overlapped LDD transistor

Inuishi, M., Mitsui, K., Komori, S., Shimizu, M., Oda, H., Mitsuhashi, J. & Tsukamoto, K., 1989 12 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 33-34 2 p.

研究成果: Conference article

11 引用 (Scopus)
1988

Deep submicron device isolation with buried insulator between source/drain polysilicon (BIPS)

Shimizu, M., Inuishi, M., Ogawa, T., Miyatake, H., Tsukamoto, K. & Akasaka, Y., 1988 12 1, : : Technical Digest - International Electron Devices Meeting. p. 96-99 4 p.

研究成果: Conference article

Novel polysilicon source/drain transistor with self-aligned silicidation.

Shimizu, M., Inuishi, M., Miyatake, H., Morita, H., Tsukamoto, K. & Akasaka, Y., 1988 12 1, : : Digest of Technical Papers - Symposium on VLSI Technology. p. 11-12 2 p.

研究成果: Conference article

1987

DOUBLE STACKED CAPACITOR WITH SELF-ALIGNED POLY SOURCE/DRAIN TRANSISTOR (DSP) CELL FOR MEGABIT DRAM.

Tsukamoto, K., Shimizu, M., Inuishi, M., Matsuda, Y., Oda, H., Morita, H., Nakajima, M., Kobayashi, K., Mashiko, Y. & Akasaka, Y., 1987 12 1, : : Technical Digest - International Electron Devices Meeting. p. 328-331 4 p.

研究成果: Conference article

5 引用 (Scopus)
1984

HIGHLY RELIABLE N-MOS PROCESS FOR ONE MEGABIT DYNAMIC RANDOM ACCESS MEMORY.

Matsukawa, T., Inuishi, M., Mitsuhashi, J., Hirayama, M., Tsukamoto, K., Uoya, S., Yoshihara, T. & Nakata, H., 1984 12 1, : : Technical Digest - International Electron Devices Meeting. p. 647-650 4 p.

研究成果: Conference article

2 引用 (Scopus)