• 847 引用
  • 14 h指数
19982020
Pureに変更を加えた場合、すぐここに表示されます。

研究成果 1998 2020

  • 847 引用
  • 14 h指数
  • 128 Conference contribution
  • 99 Article
  • 5 Chapter
  • 1 Letter

2n RRR: Improved stochastic number duplicator based on bit re-arrangement

Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 12 10, 2018 New Generation of CAS, NGCAS 2018. Institute of Electrical and Electronics Engineers Inc., p. 182-185 4 p. 8572289

研究成果: Conference contribution

flip-flops
Networks (circuits)
Flip flop circuits
output
Hyperbolic functions

A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS

Sato, H., Yanagisawa, M. & Yoshimasu, T., 2017 12 1, EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits. Institute of Electrical and Electronics Engineers Inc., 巻 2017-January. p. 1-2 2 p.

研究成果: Conference contribution

Power amplifiers
Networks (circuits)
Communication
High-level Synthesis
Controller
Controllers
Unit
Hardware Design
1 引用 (Scopus)
Code Generation
Error-correcting Codes
Clustering
Data storage equipment
One to many
5 引用 (Scopus)

A bit-write reduction method based on error-correcting codes for non-volatile memories

Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2015 3 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 496-501 6 p. 7059055

研究成果: Conference contribution

Error-correcting Codes
Reduction Method
Data storage equipment
Cell
Energy
Linear Feedback Shift Register
Seed
Grouping
ROM
Simulated annealing
2 引用 (Scopus)

Accurate automated clustering of two-dimensional data for single-nucleotide polymorphism genotyping by a combination of clustering methods: Evaluation by large-scale real data

Takitoh, S., Fujii, S., Mase, Y., Takasaki, J., Yamazaki, T., Ohnishi, Y., Yanagisawa, M., Nakamura, Y. & Kamatani, N., 2007 2 15, : : Bioinformatics. 23, 4, p. 408-413 6 p.

研究成果: Article

Single nucleotide Polymorphism
Nucleotides
Polymorphism
Clustering Methods
Single Nucleotide Polymorphism

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 250-255 6 p.

研究成果: Conference contribution

Application programs
Data storage equipment
Hardware
6 引用 (Scopus)

Acoustic tracking of sperm whales using two sets of hydrophone array

Ura, T., Bahl, R., Sakata, M., Kojima, J., Fukuchi, T., Ura, J., Nose, Y., Sugimatsu, H., Mori, K., Nakatani, T. & Yanagisawa, M., 2004, 2004 International Symposium on Underwater Technology, UT'04 - Proceedings. p. 103-107 5 p.

研究成果: Conference contribution

Hydrophones
Acoustics
Boats
Experiments
Acoustic waves
1 引用 (Scopus)

A delay variation and floorplan aware high-level synthesis algorithm with body biasing

Igawa, K., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 5 25, Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. IEEE Computer Society, 巻 2016-May. p. 75-80 6 p. 7479179

研究成果: Conference contribution

Bias voltage
Degradation
Networks (circuits)
High level synthesis
5 引用 (Scopus)
Scheduling
High level synthesis
Silicon
1 引用 (Scopus)
Logic
Boolean Networks
Minimise
Table lookup
Look-up Table
Cryptography
Hardware
Scheduling algorithms
Scheduling Algorithm
Fast Algorithm
Synthesis
Connectivity
1 引用 (Scopus)
Fast Fourier transforms

A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit

Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 1083-1086 4 p. 5774956

研究成果: Conference contribution

Fast Fourier transforms
Adders
Optical resolving power
Image resolution
Costs
Time delay
12 引用 (Scopus)
Scheduling
Error detection
High level synthesis
1 引用 (Scopus)

A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Fujiwara, K., Abe, S., Kawamura, K., Yanagisawa, M. & Togawa, N., 2015 2 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February 版 Institute of Electrical and Electronics Engineers Inc., 巻 2015-February. p. 244-247 4 p. 7032765

研究成果: Conference contribution

Field programmable gate arrays (FPGA)
Delay circuits
Costs
Scheduling
High level synthesis
High-level Synthesis
Bias voltage
Leakage
Data flow graphs
Energy
2 引用 (Scopus)
High-level Synthesis
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Module
Costs
1 引用 (Scopus)

A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration

Terada, K., Yanagisawa, M. & Togawa, N., 2015 7 27, Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 巻 2015-July. p. 2129-2132 4 p. 7169100

研究成果: Conference contribution

Scheduling
High level synthesis
1 引用 (Scopus)

A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration

Teradat, K., Yanagisawa, M. & Togawa, N., 2015 2 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February 版 Institute of Electrical and Electronics Engineers Inc., 巻 2015-February. p. 248-251 4 p. 7032766

研究成果: Conference contribution

Scheduling
High level synthesis
Hardware
Software
Unit
Application programs
Cycle
16 引用 (Scopus)
Digital Signal Processor
Digital signal processors
Application programs
kernel
Computer hardware
9 引用 (Scopus)
Digital Signal Processor
Digital signal processors
Digital signal processing
Application programs
Software System
Associative storage
Software System
Hardware
Application programs
Memory Function
1 引用 (Scopus)

A hardware/software partitioning algorithm for digital signal processor cores with two types of register files

Togawa, N., Sakurai, T., Yanagisawa, M. & Ohtsuki, T., 2000, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. p. 544-547 4 p.

研究成果: Conference contribution

Digital signal processors
Hardware
2 引用 (Scopus)
Hardware/software Partitioning
Hardware
Unit
Timing
Configuration
2 引用 (Scopus)

A hardware/software partitioning algorithm for SIMD processor cores

Tachikake, K., Togawa, N., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Institute of Electrical and Electronics Engineers Inc., 巻 2003-January. p. 135-140 6 p. 1195006

研究成果: Conference contribution

Hardware
Application programs
10 引用 (Scopus)
Learning systems
Machine Learning
Hardware
Support vector machines
Neural networks
1 引用 (Scopus)

A hardware-Trojan classification method utilizing boundary net structures

Hasegawa, K., Yanagisawa, M. & Togawa, N., 2018 3 26, 2018 IEEE International Conference on Consumer Electronics, ICCE 2018. Institute of Electrical and Electronics Engineers Inc., 巻 2018-January. p. 1-4 4 p.

研究成果: Conference contribution

Hardware
Learning systems
Hardware security
5 引用 (Scopus)
Scoring
Hardware
Benchmark
Classify
Outsourcing
Energy Levels
Electron energy levels
Energy
High-level Synthesis
Delay Time
3 引用 (Scopus)

A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 5 31, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 7482547

研究成果: Conference contribution

clocks
Field programmable gate arrays (FPGA)
Clocks
synthesis
Networks (circuits)
1 引用 (Scopus)
High-level Synthesis
Latency
List Scheduling
Interconnection
Scheduling
Data flow graphs
High-level Synthesis
Flow Graphs
Digital signal processing
Data Flow
1 引用 (Scopus)
Power Analysis
Power Consumption
Electric power utilization
Noise Reduction
Noise abatement

A high-performance circuit design algorithm using data dependent approximation

Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 12 27, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., p. 95-96 2 p. 7799750

研究成果: Conference contribution

Networks (circuits)
approximation
adding circuits
Adders
time measurement
Motion estimation
Wavelet transforms
Wavelets
High Performance
Wavelet Coefficients
Data compression
Data Compression
Glossaries
Slice
Compression
3 引用 (Scopus)

A landmark-based route recommendation method for pedestrian walking strategies

Bao, S., Nitta, T., Shindou, D., Yanagisawa, M. & Togawa, N., 2016 2 3, 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015. Institute of Electrical and Electronics Engineers Inc., p. 672-673 2 p. 7398511

研究成果: Conference contribution

landmarks
walking
recommendations
Walking
routes
1 引用 (Scopus)
Locality
Configuration
Communication
Hierarchical Networks
Multimedia Applications

A loop structure optimization targeting high-level synthesis of fast number theoretic transform

Kawamura, K., Yanagisawa, M. & Togawa, N., 2018 5 9, 2018 19th International Symposium on Quality Electronic Design, ISQED 2018. IEEE Computer Society, 巻 2018-March. p. 106-111 6 p.

研究成果: Conference contribution

Field programmable gate arrays (FPGA)
Cryptography
Program processors
Hardware
High level synthesis
3 引用 (Scopus)

A low cost and high speed CSD-based symmetric transpose block FIR implementation

Ye, J., Shi, Y., Togawa, N. & Yanagisawa, M., 2018 1 8, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. IEEE Computer Society, 巻 2017-October. p. 311-314 4 p.

研究成果: Conference contribution

Costs
Reusability
Digital signal processing
Energy utilization
Processing
Soft Error
Trigger
Power Consumption
Electric power utilization
Double Sampling
1 引用 (Scopus)

A low-power soft error tolerant latch scheme

Tajima, S., Shi, Y., Togawa, N. & Yanagisawa, M., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516885

研究成果: Conference contribution

Electric power utilization
Integrated circuits
Capacitance
Networks (circuits)
Electric potential
2 引用 (Scopus)
Coloring
Heuristic algorithms
Electric power utilization
System-on-chip
1 引用 (Scopus)

A multiple cyclic-route generation method for strolling based on point-of-interests

Nishimura, T., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2018 12 13, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2018. IEEE Computer Society, 巻 2018-September. 8576185

研究成果: Conference contribution