年単位の研究成果
研究成果 1998 2020
Article
A bitwidth-aware high-level synthesis algorithm using operation chainings for tiled-DR architectures
Terada, K., Yanagisawa, M. & Togawa, N., 2017 12 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 12, p. 2911-2924 14 p.研究成果: Article
High-level Synthesis
Controller
Controllers
Unit
Hardware Design
1
引用
(Scopus)
A bit-write-reducing and error-correcting code generation method by clustering ECC codewords for non-volatile memories
Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 12 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2398-2411 14 p.研究成果: Article
Code Generation
Error-correcting Codes
Clustering
Data storage equipment
One to many
A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation
Shi, Y., Zhang, Z., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2003 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3056-3062 7 p.研究成果: Article
Linear Feedback Shift Register
Seed
Grouping
ROM
Simulated annealing
2
引用
(Scopus)
Accurate automated clustering of two-dimensional data for single-nucleotide polymorphism genotyping by a combination of clustering methods: Evaluation by large-scale real data
Takitoh, S., Fujii, S., Mase, Y., Takasaki, J., Yamazaki, T., Ohnishi, Y., Yanagisawa, M., Nakamura, Y. & Kamatani, N., 2007 2 15, ： : Bioinformatics. 23, 4, p. 408-413 6 p.研究成果: Article
Single nucleotide Polymorphism
Nucleotides
Polymorphism
Clustering Methods
Single Nucleotide Polymorphism
5
引用
(Scopus)
A delay-variation-aware high-level synthesis algorithm for RDR architectures
Hagio, Y., Yanagisawa, M. & Togawa, N., 2014, ： : IPSJ Transactions on System LSI Design Methodology. 7, p. 81-90 10 p.研究成果: Article
Scheduling
High level synthesis
Silicon
1
引用
(Scopus)
A depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured LUTs
Togawa, N., Ara, K., Yanagisawa, M. & Ohtsuki, T., 1999, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 3, p. 473-481 9 p.研究成果: Article
Logic
Boolean Networks
Minimise
Table lookup
Look-up Table
A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier
Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, ： : IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.研究成果: Article
Cryptography
Hardware
A fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis
Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1998, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 6, p. 1231-1241 11 p.研究成果: Article
Scheduling algorithms
Scheduling Algorithm
Fast Algorithm
Synthesis
Connectivity
1
引用
(Scopus)
A fast selector-based subtract-multiplication unit and its application to butterfly unit
Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, ： : IPSJ Transactions on System LSI Design Methodology. 4, p. 60-69 10 p.研究成果: Article
Fast Fourier transforms
A fastweighted adder by reducing partial product for reconstruction in super-resolution
Yoshihara, H., Yanagisawa, M. & Togawa, N., 2012, ： : IPSJ Transactions on System LSI Design Methodology. 5, p. 96-105 10 p.研究成果: Article
Adders
Optical resolving power
Image resolution
Costs
Time delay
12
引用
(Scopus)
A fault-secure high-level synthesis algorithm for RDR architectures
Tanaka, S., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, ： : IPSJ Transactions on System LSI Design Methodology. 4, p. 150-165 16 p.研究成果: Article
Scheduling
Error detection
High level synthesis
A floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation
Igawa, K., Yanagisawa, M. & Togawa, N., 2017 7 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1439-1451 13 p.研究成果: Article
High-level Synthesis
Bias voltage
Leakage
Data flow graphs
Energy
2
引用
(Scopus)
A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting FPGA designs
Fujiwara, K., Kawamura, K., Abe, S. Y., Yanagisawa, M. & Togawa, N., 2015 7 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1392-1405 14 p.研究成果: Article
High-level Synthesis
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Module
Costs
A hardware/software cosynthesis algorithm for processors with heterogeneous datapaths
Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 4, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 4, p. 830-836 7 p.研究成果: Article
Hardware
Software
Unit
Application programs
Cycle
16
引用
(Scopus)
A hard ware/S oft ware cosynthesis system for digital signal processor cores
Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1999, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 11, p. 2325-2327 3 p.研究成果: Article
Digital Signal Processor
Digital signal processors
Application programs
kernel
Computer hardware
9
引用
(Scopus)
A hardware/software cosynthesis system for digital signal processor cores with two types of register files
Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2000, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 3, p. 442-451 10 p.研究成果: Article
Digital Signal Processor
Digital signal processors
Digital signal processing
Application programs
Software System
A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories
Togawa, N., Totsuka, T., Wakui, T., Yanagisawa, M. & Ohtsuki, T., 2003 5, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 5, p. 1082-1092 11 p.研究成果: Article
Associative storage
Software System
Hardware
Application programs
Memory Function
2
引用
(Scopus)
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions
Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2003 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3218-3224 7 p.研究成果: Article
Hardware/software Partitioning
Hardware
Unit
Timing
Configuration
10
引用
(Scopus)
A hardware-trojan classification method using machine learning at gate-level netlists based on Trojan features
Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 7 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1427-1438 12 p.研究成果: Article
Learning systems
Machine Learning
Hardware
Support vector machines
Neural networks
5
引用
(Scopus)
A hardware-trojans identifying method based on trojan net scoring at gate-level netlists
Oya, M., Shi, Y., Yamashita, N., Okamura, T., Tsunoo, Y., Goto, S., Yanagisawa, M. & Togawa, N., 2015 12 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2537-2546 10 p.研究成果: Article
Scoring
Hardware
Benchmark
Classify
Outsourcing
A high-level energy-optimizing algorithm for system VLSIs based on area/time/power estimation
Noda, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2655-2666 12 p.研究成果: Article
Energy Levels
Electron energy levels
Energy
High-level Synthesis
Delay Time
1
引用
(Scopus)
A high-level synthesis algorithm with inter-island distance based operation chainings for RDR architectures
Terada, K., Yanagisawa, M. & Togawa, N., 2015 7 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1366-1375 10 p.研究成果: Article
High-level Synthesis
Latency
List Scheduling
Interconnection
Scheduling
A high-level synthesis system for digital signal processing based on data-flow graph enumeration
Togawa, N., Hisakl, T., Yanagisawa, M. & Ohtsuku, T., 1998, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2563-2575 13 p.研究成果: Article
Data flow graphs
High-level Synthesis
Flow Graphs
Digital signal processing
Data Flow
1
引用
(Scopus)
A highly-adaptable and small-sized in-field power analyzer for low-power IoT devices
Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 12 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2348-2362 15 p.研究成果: Article
Power Analysis
Power Consumption
Electric power utilization
Noise Reduction
Noise abatement
A high performance embedded wavelet video coder
Zhao, T., Yanagisawa, M. & Ohtsuki, T., 2000, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 6, p. 979-986 8 p.研究成果: Article
Motion estimation
Wavelet transforms
Wavelets
High Performance
Wavelet Coefficients
A high-speed trace-driven cache configuration simulator for dual-core processor L1 caches
Tawada, M., Yanagisawa, M. & Togawa, N., 2013 6, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 6, p. 1283-1292 10 p.研究成果: Article
Cache
Data structures
Simulator
High Speed
Simulators
A hybrid dictionary test data compression for multiscan-based designs
Shi, Y., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2004 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3193-3199 7 p.研究成果: Article
Data compression
Data Compression
Glossaries
Slice
Compression
1
引用
(Scopus)
A locality-aware hybrid NoC configuration algorithm utilizing the communication volume among IP cores
Lee, S., Yanagisawa, M. & Togawa, N., 2012 9, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E95-A, 9, p. 1538-1549 12 p.研究成果: Article
Locality
Configuration
Communication
Hierarchical Networks
Multimedia Applications
A low power soft error hardened latch with schmitt-trigger-based C-Element
Tajima, S., Togawa, N., Yanagisawa, M. & Shi, Y., 2018 7 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1025-1034 10 p.研究成果: Article
Soft Error
Trigger
Power Consumption
Electric power utilization
Double Sampling
A multiple cyclic-route generation method with route length constraint considering point-of-interests
Nishimura, T., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019 4 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 4, p. 641-653 13 p.研究成果: Article
Reference Point
User Preferences
Search Methods
3
引用
(Scopus)
An algorithm and a flexible architecture for fast block-matching motion estimation
Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2603-2611 9 p.研究成果: Article
Block Matching
Motion Estimation
Motion estimation
Hardware Architecture
Computer hardware description languages
1
引用
(Scopus)
An area/time optimizing algorithm in high-level synthesis of control-based hardwares
Togawa, N., Ienaga, M., Yanagisawa, M. & Ohsuki, T., 2001 5, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 5, p. 1166-1176 11 p.研究成果: Article
High-level Synthesis
Hardware
Application programs
Graph in graph theory
Hardware Architecture
3
引用
(Scopus)
An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead
Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 7 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1406-1418 13 p.研究成果: Article
Prediction Error
Insertion
Timing
Networks (circuits)
Checkpoint
1
引用
(Scopus)
An energy-efficient floorplan driven high-level synthesis algorithm for multiple clock domains design
Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2015 7 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1376-1391 16 p.研究成果: Article
High-level Synthesis
Energy Efficient
Clocks
Interconnect
Energy Saving
5
引用
(Scopus)
An Evaluation of Hand-Force Prediction Using Artificial Neural-Network Regression Models of Surface EMG Signals for Handwear Devices
Yokoyama, M., Koyama, R. & Yanagisawa, M., 2017 1 1, ： : Journal of Sensors. 2017, 3980906.研究成果: Article
Electromyography
regression analysis
Neural networks
evaluation
Dynamometers
A new hardware/software partitioning algorithm for DSP processor cores with two types of register files
Togawa, N., Sakurai, T., Yanagisawa, M. & Ohsuki, T., 2001 11, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2802-2807 6 p.研究成果: Article
Hardware/software Partitioning
Hardware
Unit
Digital Signal Processor
Digital signal processors
An FPGA implementation method based on distributed-register architectures
Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2019 2 1, ： : IPSJ Transactions on System LSI Design Methodology. 12, p. 38-41 4 p.研究成果: Article
公開
Field programmable gate arrays (FPGA)
Networks (circuits)
An FPGA layout reconfiguration algorithm based on global routes for engineering changes in system design specifications
Togawa, N., Hagi, K., Yanagisawa, M. & Ohtsuki, T., 1998, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 5, p. 873-884 12 p.研究成果: Article
Table lookup
Look-up Table
Reconfiguration
Field Programmable Gate Array
System Design
An l1 cache design space exploration system for embedded applications
Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 6, p. 1442-1453 12 p.研究成果: Article
Design Space Exploration
Cache
Data storage equipment
Embedded systems
Configuration
4
引用
(Scopus)
Area and delay estimation in hardware/software cosynthesis for digital signal processor cores
Togawa, N., Kataoka, Y., Miyaoka, Y., Yanagisawa, M. & Ohsuki, T., 2001 11, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2639-2647 9 p.研究成果: Article
Delay Estimation
Digital Signal Processor
Digital signal processors
Hardware
Software
A relaxed bit-write-reducing and error-correcting code for non-volatile memories
Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 7 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1045-1052 8 p.研究成果: Article
Error-correcting Codes
Data storage equipment
Systematic Error
Crosstalk
Error Correction
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions
Togawa, N., Kasahara, K., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3099-3109 11 p.研究成果: Article
Simulator
Simulators
Generator
Hardware
Application programs
1
引用
(Scopus)
A robust indoor/outdoor detection method based on spatial and temporal features of sparse GPS measured positions
Iwata, S., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019 1 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 6, p. 860-865 6 p.研究成果: Article
Global positioning system
Classifiers
Random Forest
Learning systems
Classify
1
引用
(Scopus)
A safe and comprehensive route finding algorithm for pedestrians based on lighting and landmark conditions
Bao, S., Nitta, T., Yanagisawa, M. & Togawa, N., 2017 11 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 11, p. 2439-2450 12 p.研究成果: Article
Landmarks
Lighting
Count
Safety
Algorithm Design
30
引用
(Scopus)
A scan-based attack based on discriminators for AES cryptosystems
Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3229-3237 9 p.研究成果: Article
Discriminators
Cryptosystem
Cryptography
Attack
Networks (circuits)
3
引用
(Scopus)
A secure test technique for pipelined advanced encryption standard
Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 3, ： : IEICE Transactions on Information and Systems. E91-D, 3, p. 776-780 5 p.研究成果: Article
Cryptography
Failure analysis
Testing
A selective scan chain reconfiguration through run-length coding for test data compression and scan power reduction
Shi, Y., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2004 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3208-3214 7 p.研究成果: Article
Run Length
Data compression
Data Compression
Reconfiguration
Coding
1
引用
(Scopus)
A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition
Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005 7, ： : IEICE Transactions on Information and Systems. E88-D, 7, p. 1340-1349 10 p.研究成果: Article
Decomposition
A simultaneous placement and global routing algorithm for FPGAs with power optimization
Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1999 2, ： : Journal of Circuits, Systems and Computers. 9, 1-2, p. 99-112 14 p.研究成果: Article
Routing algorithms
Field programmable gate arrays (FPGA)
Electric power utilization
Networks (circuits)
2
引用
(Scopus)
A stayed location estimation method for sparse GPS positioning information based on positioning accuracy and short-time cluster removal
Iwata, S., Nitta, T., Takayama, T., Yanagisawa, M. & Togawa, N., 2018 5 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 5, p. 831-843 13 p.研究成果: Article
Location Estimation
Positioning
Global positioning system
Mobile devices
Mobile Devices