• 847 引用
  • 14 h指数
19982020
Pureに変更を加えた場合、すぐここに表示されます。

研究成果 1998 2020

  • 847 引用
  • 14 h指数
  • 128 Conference contribution
  • 99 Article
  • 5 Chapter
  • 1 Letter
2017
Extractor
Wire
Evaluation
Networks (circuits)
Partitioning
1 引用 (Scopus)

Hardware Trojan detection and classification based on steady state learning

Oya, M., Yanagisawa, M. & Togawa, N., 2017 9 19, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., p. 215-220 6 p. 8046225

研究成果: Conference contribution

Testing
Networks (circuits)
Hardware security
21 引用 (Scopus)

Hardware Trojans classification for gate-level netlists using multi-layer neural networks

Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 9 19, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., p. 227-232 6 p. 8046227

研究成果: Conference contribution

Multilayer neural networks
Hardware
Outsourcing
Learning systems
Integrated circuit design

Implementation evaluation of scan-based attack against a Trivium cipher circuit

Oku, D., Yanagisawa, M. & Togawa, N., 2017 1 3, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., p. 220-223 4 p. 7803938

研究成果: Conference contribution

Field programmable gate arrays (FPGA)
Networks (circuits)
Processing
2 引用 (Scopus)

Indoor navigation based on real-Time direction information generation using wearable glasses

Iwanaji, R., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2017 1 3, 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016. Institute of Electrical and Electronics Engineers Inc., 7804754

研究成果: Conference contribution

Navigation systems
navigation
Navigation
Glass
landmarks

Personalized one-day travel with multi-nearby-landmark recommendation

Bao, S., Yanagisawa, M. & Togawa, N., 2017 12 14, 2017 IEEE 7th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017. IEEE Computer Society, 巻 2017-September. p. 239-242 4 p.

研究成果: Conference contribution

Planning
Industry
1 引用 (Scopus)

Rotator-based multiplexer network synthesis for field-data extractors

Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2017 4 19, Proceedings - 29th IEEE International System on Chip Conference, SOCC 2016. IEEE Computer Society, p. 194-199 6 p. 7905464

研究成果: Conference contribution

Wire
17 引用 (Scopus)

Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier

Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 9 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050827

研究成果: Conference contribution

Feature extraction
Classifiers
Learning systems
Outsourcing
Hardware
3 引用 (Scopus)
Random Forest
Feature Extraction
Learning systems
Feature extraction
Hardware
2016
1 引用 (Scopus)
Code Generation
Error-correcting Codes
Clustering
Data storage equipment
One to many
1 引用 (Scopus)

A delay variation and floorplan aware high-level synthesis algorithm with body biasing

Igawa, K., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 5 25, Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. IEEE Computer Society, 巻 2016-May. p. 75-80 6 p. 7479179

研究成果: Conference contribution

Bias voltage
Degradation
Networks (circuits)
High level synthesis
3 引用 (Scopus)

A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 5 31, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 7482547

研究成果: Conference contribution

clocks
Field programmable gate arrays (FPGA)
Clocks
synthesis
Networks (circuits)
1 引用 (Scopus)
Power Analysis
Power Consumption
Electric power utilization
Noise Reduction
Noise abatement

A high-performance circuit design algorithm using data dependent approximation

Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 12 27, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., p. 95-96 2 p. 7799750

研究成果: Conference contribution

Networks (circuits)
approximation
adding circuits
Adders
time measurement
3 引用 (Scopus)

A landmark-based route recommendation method for pedestrian walking strategies

Bao, S., Nitta, T., Shindou, D., Yanagisawa, M. & Togawa, N., 2016 2 3, 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015. Institute of Electrical and Electronics Engineers Inc., p. 672-673 2 p. 7398511

研究成果: Conference contribution

landmarks
walking
recommendations
Walking
routes
1 引用 (Scopus)

A low-power soft error tolerant latch scheme

Tajima, S., Shi, Y., Togawa, N. & Yanagisawa, M., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516885

研究成果: Conference contribution

Electric power utilization
Integrated circuits
Capacitance
Networks (circuits)
Electric potential
2 引用 (Scopus)

A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures

Igawa, K., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 2 12, International System on Chip Conference. IEEE Computer Society, 巻 2016-February. p. 7-12 6 p. 7406898

研究成果: Conference contribution

Scheduling
High level synthesis
3 引用 (Scopus)

A safe and comprehensive route finding method for pedestrian based on lighting and landmark

Bao, S., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 12 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800525

研究成果: Conference contribution

landmarks
illuminating
Lighting
routes
fear
1 引用 (Scopus)

A visible corner-landmark based route finding algorithm for pedestrian navigation

Takeda, K., Nitta, T., Shindou, D., Yanagisawa, M. & Togawa, N., 2016 2 3, 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015. Institute of Electrical and Electronics Engineers Inc., p. 601-602 2 p. 7398498

研究成果: Conference contribution

landmarks
navigation
Navigation
routes
Visibility
1 引用 (Scopus)
Extractor
Partitioning
Stream Processing
Consecutive
Count
2 引用 (Scopus)

Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories

Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 1 5, 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., p. 682-689 8 p. 7372636

研究成果: Conference contribution

Data storage equipment
Code generation
Crosstalk
Energy utilization
Radiation
3 引用 (Scopus)

Clock skew estimate modeling for FPGA high-level synthesis and its application

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516905

研究成果: Conference contribution

Field programmable gate arrays (FPGA)
Clocks
High level synthesis
Networks (circuits)
2 引用 (Scopus)

Comprehensive deformed map generation for wristwatch-type wearable devices based on landmark-based partitioning

Kono, K., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 12 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800432

研究成果: Conference contribution

landmarks
routes
wrist
Information services
partitions
24 引用 (Scopus)

Hardware Trojans classification for gate-level netlists based on machine learning

Hasegawa, K., Oya, M., Yanagisawa, M. & Togawa, N., 2016 10 20, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016. Institute of Electrical and Electronics Engineers Inc., p. 203-206 4 p. 7604700

研究成果: Conference contribution

Support vector machines
Learning systems
Hardware
Classifiers
Hardware security
6 引用 (Scopus)
Quantitative Evaluation
Pattern matching
Pattern Matching
Hardware
Benchmark
2 引用 (Scopus)

Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation

Igarashi, K., Yanagisawa, M. & Togawa, N., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7517027

研究成果: Conference contribution

Field programmable gate arrays (FPGA)
Networks (circuits)
Pixels
Delay circuits
Data storage equipment

Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation

Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516962

研究成果: Conference contribution

Monitoring
4 引用 (Scopus)

In-situ Trojan authentication for invalidating hardware-Trojan functions

Oya, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 5 25, Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. IEEE Computer Society, 巻 2016-May. p. 152-157 6 p. 7479192

研究成果: Conference contribution

Authentication
Hardware
Hardware security
Networks (circuits)
Clocks
Field programmable gate arrays (FPGA)
registers
platforms
Wave filters
Networks (circuits)
2 引用 (Scopus)

Muscle analysis of hand and forearm during tapping using surface electromyography

Yokoyama, M., Koyama, R. & Yanagisawa, M., 2016 2 3, 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015. Institute of Electrical and Electronics Engineers Inc., p. 595-598 4 p. 7398505

研究成果: Conference contribution

electromyography
forearm
Electromyography
muscles
Forearm
3 引用 (Scopus)

Partitioning-based multiplexer network synthesis for field-data extractors

Ito, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2016 2 12, International System on Chip Conference. IEEE Computer Society, 巻 2016-February. p. 263-268 6 p. 7406960

研究成果: Conference contribution

Engines

Pedestrian navigation based on landmark recognition using glass-type wearable devices

Yano, R., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 12 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800433

研究成果: Conference contribution

landmarks
Navigation systems
navigation
Navigation
Glass

Redesign for untrusted gate-level netlists

Oya, M., Yanagisawa, M. & Togawa, N., 2016 10 20, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016. Institute of Electrical and Electronics Engineers Inc., p. 219-220 2 p. 7604706

研究成果: Conference contribution

Hardware
Pattern matching
Chemical activation

Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 7 29, ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 巻 2016-July. p. 978-981 4 p. 7527406

研究成果: Conference contribution

Noise abatement
Electric power utilization
Measurement errors
Cryptography
Energy utilization
2 引用 (Scopus)

Small-sized and noise-reducing power analyzer design for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516927

研究成果: Conference contribution

Cryptography
Light emitting diodes
Microprocessor chips
Synchronization
Electric power utilization
2015
5 引用 (Scopus)

A bit-write reduction method based on error-correcting codes for non-volatile memories

Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2015 3 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 496-501 6 p. 7059055

研究成果: Conference contribution

Error-correcting Codes
Reduction Method
Data storage equipment
Cell
Energy
1 引用 (Scopus)

A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Fujiwara, K., Abe, S., Kawamura, K., Yanagisawa, M. & Togawa, N., 2015 2 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February 版 Institute of Electrical and Electronics Engineers Inc., 巻 2015-February. p. 244-247 4 p. 7032765

研究成果: Conference contribution

Field programmable gate arrays (FPGA)
Delay circuits
Costs
Scheduling
High level synthesis
2 引用 (Scopus)
High-level Synthesis
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Module
Costs
1 引用 (Scopus)

A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration

Terada, K., Yanagisawa, M. & Togawa, N., 2015 7 27, Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 巻 2015-July. p. 2129-2132 4 p. 7169100

研究成果: Conference contribution

Scheduling
High level synthesis
1 引用 (Scopus)

A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration

Teradat, K., Yanagisawa, M. & Togawa, N., 2015 2 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February 版 Institute of Electrical and Electronics Engineers Inc., 巻 2015-February. p. 248-251 4 p. 7032766

研究成果: Conference contribution

Scheduling
High level synthesis
5 引用 (Scopus)
Scoring
Hardware
Benchmark
Classify
Outsourcing
1 引用 (Scopus)
High-level Synthesis
Latency
List Scheduling
Interconnection
Scheduling
1 引用 (Scopus)

An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction

Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 2 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February 版 Institute of Electrical and Electronics Engineers Inc., 巻 2015-February. p. 300-303 4 p. 7032779

研究成果: Conference contribution

Monitoring
Networks (circuits)
Timing circuits
Error correction
3 引用 (Scopus)
Prediction Error
Insertion
Timing
Networks (circuits)
Checkpoint
1 引用 (Scopus)
High-level Synthesis
Energy Efficient
Clocks
Interconnect
Energy Saving
43 引用 (Scopus)

A score-based classification method for identifying Hardware-Trojans at gate-level netlists

Oya, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 4 22, Proceedings -Design, Automation and Test in Europe, DATE. Institute of Electrical and Electronics Engineers Inc., 巻 2015-April. p. 465-470 6 p. 7092434

研究成果: Conference contribution

Hardware
Semiconductor materials
3 引用 (Scopus)

A write-reducing and error-correcting code generation method for non-volatile memories

Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2015 2 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February 版 Institute of Electrical and Electronics Engineers Inc., 巻 2015-February. p. 304-307 4 p. 7032780

研究成果: Conference contribution

Data storage equipment
Hamming distance
Crosstalk
Radiation
Code generation
2 引用 (Scopus)
Hamming distance
Code Generation
Hamming Distance
Minimum Distance
Limiting
2 引用 (Scopus)
Code Generation
Data storage equipment
Error-correcting Codes
Energy
Static random access storage

Fast source optimization by clustering algorithm based on lithography properties

Tawada, M., Hashimoto, T., Sakanushi, K., Nojima, S., Kotani, T., Yanagisawa, M. & Togawa, N., 2015, Proceedings of SPIE - The International Society for Optical Engineering. SPIE, 巻 9427. 94270K

研究成果: Conference contribution

Photoresists
Lithography
Clustering algorithms
Clustering Algorithm
Photoresist