• 847 引用
  • 14 h指数
19982020
Pureに変更を加えた場合、すぐここに表示されます。

研究成果 1998 2020

  • 847 引用
  • 14 h指数
  • 128 Conference contribution
  • 99 Article
  • 5 Chapter
  • 1 Letter
2015
1 引用 (Scopus)

Scan-based side-channel attack against symmetric key ciphers using scan signatures

Fujishiro, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 9 30, Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., p. 309-312 4 p. 7285112

研究成果: Conference contribution

Cryptography
Information use
Side channel attack
3 引用 (Scopus)

Scan-based side-channel attack on Camellia cipher using scan signatures

Hang, H., Fujishiro, M., Kodera, H., Yanagisawa, M. & Togawa, N., 2015 2 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February 版 Institute of Electrical and Electronics Engineers Inc., 巻 2015-February. p. 252-255 4 p. 7032767

研究成果: Conference contribution

Cryptography
Hardware
Side channel attack
1 引用 (Scopus)
Side Channel Attacks
Block Cipher
Signature
Cryptography
Chip
4 引用 (Scopus)

Secure scan design using improved random order and its evaluations

Oya, M., Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 2 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February 版 Institute of Electrical and Electronics Engineers Inc., 巻 2015-February. p. 555-558 4 p. 7032842

研究成果: Conference contribution

Discrete Fourier transforms
Networks (circuits)
2014
5 引用 (Scopus)
Scheduling
High level synthesis
Silicon
Clocks
Energy utilization
High level synthesis
7 引用 (Scopus)

Linear and bi-linear interpolation circuits using selector logics and their evaluations

Shio, M., Yanagisawa, M. & Togawa, N., 2014, Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., p. 1436-1439 4 p. 6865415

研究成果: Conference contribution

Interpolation
Networks (circuits)
Adders
5 引用 (Scopus)
Stream Cipher
Shift registers
Signature
Attack
Internal
3 引用 (Scopus)

Scan-based attack on the LED block cipher using scan signatures

Fujishiro, M., Yanagisawa, M. & Togawa, N., 2014, Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., p. 1460-1463 4 p. 6865421

研究成果: Conference contribution

Cryptography
Computer hardware
3 引用 (Scopus)
Side Channel Attacks
Block Cipher
Encryption
Cryptography
Signature

Throughput driven check point selection in suspicious timing error prediction based designs

Igarashi, H., Shi, Y., Yanagisawa, M. & Togawa, N., 2014, 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings. IEEE Computer Society, 6820280

研究成果: Conference contribution

Throughput
Networks (circuits)

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533808

研究成果: Conference contribution

Electric potential
Energy conservation
Scheduling
High level synthesis

A partial redundant fault-secure high-level synthesis algorithm for RDR architectures

Kawamura, K., Tanaka, S., Yanagisawa, M. & Togawa, N., 2013, Proceedings - IEEE International Symposium on Circuits and Systems. p. 1736-1739 4 p. 6572200

研究成果: Conference contribution

Scheduling
High level synthesis
1 引用 (Scopus)
High-level Synthesis
Chip
Interconnect
Energy Consumption
Energy utilization
1 引用 (Scopus)

Concurrent faulty clock detection for crypto circuits against clock glitch based DFA

Igarashi, H., Shi, Y., Yanagisawa, M. & Togawa, N., 2013, Proceedings - IEEE International Symposium on Circuits and Systems. p. 1432-1435 4 p. 6572125

研究成果: Conference contribution

Clocks
Networks (circuits)
Side channel attack
Monitoring
1 引用 (Scopus)

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Matsuno, S., Tawada, M., Yanagisawa, M., Kimura, S., Togawa, N. & Sugibayashi, T., 2013, Proceedings of International Conference on ASIC. IEEE Computer Society, 6811826

研究成果: Conference contribution

Static random access storage
Energy utilization
Data storage equipment
Memory architecture
2 引用 (Scopus)
High-level Synthesis
Voltage
Electric potential
Floorplanning
Energy Saving
2 引用 (Scopus)

High-level synthesis with post-silicon delay tuning for RDR architectures

Hagio, Y., Yanagisawa, M. & Togawa, N., 2013, ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, p. 194-197 4 p. 6863970

研究成果: Conference contribution

Tuning
Scheduling
Silicon
High level synthesis
2 引用 (Scopus)
Cryptography
2 引用 (Scopus)

Scan-based attack against Trivium stream cipher independent of scan structure

Fujishiro, M., Yanagisawa, M. & Togawa, N., 2013, Proceedings of International Conference on ASIC. IEEE Computer Society, 6811855

研究成果: Conference contribution

Shift registers
Side channel attack
14 引用 (Scopus)

Secure scan design with dynamically configurable connection

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2013, Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC. IEEE Computer Society, p. 256-262 7 p. 6820873

研究成果: Conference contribution

Networks (circuits)
Testing
14 引用 (Scopus)

Suspicious timing error prediction with in-cycle clock gating

Shi, Y., Igarashi, H., Togawa, N. & Yanagisawa, M., 2013, Proceedings - International Symposium on Quality Electronic Design, ISQED. p. 335-340 6 p. 6523631

研究成果: Conference contribution

Clocks
Networks (circuits)
Error detection
Energy efficiency
Electric power utilization
2012
Adders
Optical resolving power
Image resolution
Costs
Time delay
1 引用 (Scopus)
Locality
Configuration
Communication
Hierarchical Networks
Multimedia Applications
8 引用 (Scopus)

An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures

Abe, S. Y., Yanagisawa, M. & Togawa, N., 2012, ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems. p. 576-579 4 p. 6272096

研究成果: Conference contribution

Energy conservation
Electric potential
Scheduling
Controllers
High level synthesis
5 引用 (Scopus)

AUV navigation around jacket structures I: Relative localization based on multi-sensor fusion

Maki, T., Mizushima, H., Ura, T., Sakamaki, T. & Yanagisawa, M., 2012 3 9, : : Journal of Marine Science and Technology (Japan). 17, 3, p. 330-339 10 p.

研究成果: Article

Autonomous underwater vehicles
Sensor data fusion
autonomous underwater vehicle
navigation
Navigation
25 引用 (Scopus)

Dynamically changeable secure scan architecture against scan-based side channel attack

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2012, ISOCC 2012 - 2012 International SoC Design Conference. p. 155-158 4 p. 6407063

研究成果: Conference contribution

Networks (circuits)
Design for testability
Side channel attack
13 引用 (Scopus)
Energy conservation
Electric potential
Semiconductor devices
Energy efficiency
Scheduling
2 引用 (Scopus)

Energy-efficient high-level synthesis for HDR architectures with clock gating

Akasaka, H., Yanagisawa, M. & Togawa, N., 2012, ISOCC 2012 - 2012 International SoC Design Conference. p. 135-138 4 p. 6407058

研究成果: Conference contribution

Clocks
Energy utilization
High level synthesis
Electric potential
3 引用 (Scopus)

Integrating wearable sensor technology into project-management process

Ara, K., Akitomi, T., Sato, N., Takahashi, K., Maeda, H., Yano, K. & Yanagisawa, M., 2012, : : Journal of Information Processing. 20, 2, p. 406-418 13 p.

研究成果: Article

Project management
Communication
Sensors
Personnel
Monitoring
14 引用 (Scopus)
Networks (circuits)
synthesis
clocks
iteration
High level synthesis
13 引用 (Scopus)

Scan-based attack against des cryptosystems using scan signatures

Kodera, H., Yanagisawa, M. & Togawa, N., 2012, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 599-602 4 p. 6419106

研究成果: Conference contribution

Cryptography
Side channel attack
Countermeasures
Side Channel Attacks
Attack
Hardware Implementation
Hardware
6 引用 (Scopus)

State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2012, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 607-610 4 p. 6419108

研究成果: Conference contribution

Flip flop circuits
Design for testability
Networks (circuits)
Side channel attack
1 引用 (Scopus)

Weighted adders with selector logics for super-resolution and its FPGA-based evaluation

Yoshihara, H., Yanagisawa, M. & Togawa, N., 2012, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 603-606 4 p. 6419107

研究成果: Conference contribution

Adders
Field programmable gate arrays (FPGA)
Networks (circuits)
Costs
2011
1 引用 (Scopus)
Fast Fourier transforms
12 引用 (Scopus)
Scheduling
Error detection
High level synthesis
Embedded systems
Simulators
Hardware
Costs
4 引用 (Scopus)

Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies

Tawada, M., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 247-250 4 p. 5783622

研究成果: Conference contribution

Embedded systems
Simulators
Hardware
Costs
Experiments
Capacitance
Greedy Algorithm
Decoupling
Chip
Voltage
3 引用 (Scopus)
Network Design
Greedy Algorithm
Optimization Algorithm
Voltage
Electric wiring
6 引用 (Scopus)
Cryptography
Networks (circuits)
Public key cryptography
Monitoring
Testing
3 引用 (Scopus)
configurations
Embedded systems
simulation
Simulators
central processing units
2010

A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit

Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 1083-1086 4 p. 5774956

研究成果: Conference contribution

Fast Fourier transforms
3 引用 (Scopus)

BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers

Lee, S., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 712-715 4 p. 5774825

研究成果: Conference contribution

Routers
Scalability
Communication
Network-on-chip
18 引用 (Scopus)

Localization of sperm whales in a group using clicks received at two separated short baseline arrays

Hirotsu, R., Yanagisawa, M., Ura, T., Sakata, M., Sugimatsu, H., Kojima, J. & Bahl, R., 2010, : : Journal of the Acoustical Society of America. 127, 1, p. 133-147 15 p.

研究成果: Article

whales
underwater trajectories
lists
arrivals
Localization
4 引用 (Scopus)

Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. p. 921-924 4 p. 5537401

研究成果: Conference contribution

Controllers
Scheduling
High level synthesis