• 847 引用
  • 14 h指数
19982020
Pureに変更を加えた場合、すぐここに表示されます。

研究成果 1998 2020

  • 847 引用
  • 14 h指数
  • 128 Conference contribution
  • 99 Article
  • 5 Chapter
  • 1 Letter
2004
Thread
Partitioning
Optimization
Networks (circuits)
High-level Synthesis
3 引用 (Scopus)

Instruction set and functional unit synthesis for SIMD processor cores

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 743-750 8 p.

研究成果: Conference contribution

Decomposition
1 引用 (Scopus)

Reducing test data volume for multiscan-based designs through single/sequence mixed encoding

Shi, Y., Kimura, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Midwest Symposium on Circuits and Systems. 巻 2.

研究成果: Conference contribution

Data compression
Glossaries
Synchronization
Costs
System-on-chip
2003
Linear Feedback Shift Register
Seed
Grouping
ROM
Simulated annealing
Associative storage
Software System
Hardware
Application programs
Memory Function
2 引用 (Scopus)
Hardware/software Partitioning
Hardware
Unit
Timing
Configuration
2 引用 (Scopus)

A hardware/software partitioning algorithm for SIMD processor cores

Tachikake, K., Togawa, N., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Institute of Electrical and Electronics Engineers Inc., 巻 2003-January. p. 135-140 6 p. 1195006

研究成果: Conference contribution

Hardware
Application programs
Simulator
Simulators
Generator
Hardware
Application programs
2002
Energy Levels
Electron energy levels
Energy
High-level Synthesis
Delay Time
3 引用 (Scopus)
Block Matching
Motion Estimation
Motion estimation
Hardware Architecture
Computer hardware description languages

An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions

Miyaoka, Y., Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Institute of Electrical and Electronics Engineers Inc., 巻 1. p. 171-176 6 p. 1114930

研究成果: Conference contribution

Hardware
4 引用 (Scopus)
Power System
Power Consumption
Clocks
Electric power utilization
High-level Synthesis
4 引用 (Scopus)

VLSI architecture for a flexible motion estimation with parameters

Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002, Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., p. 452-457 6 p. 994962

研究成果: Conference contribution

Motion estimation
Computer hardware description languages
Reconfigurable architectures
Computer hardware
Electric power utilization
2001
1 引用 (Scopus)
High-level Synthesis
Hardware
Application programs
Graph in graph theory
Hardware Architecture
Hardware/software Partitioning
Hardware
Unit
Digital Signal Processor
Digital signal processors
6 引用 (Scopus)

Area/delay estimation for digital signal processor cores

Miyaoka, Y., Kataoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2001, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Institute of Electrical and Electronics Engineers Inc., 巻 2001-January. p. 156-161 6 p. 913297

研究成果: Conference contribution

Digital signal processors
Hardware
Application programs
4 引用 (Scopus)
Delay Estimation
Digital Signal Processor
Digital signal processors
Hardware
Software
2000
9 引用 (Scopus)
Digital Signal Processor
Digital signal processors
Digital signal processing
Application programs
Software System
1 引用 (Scopus)

A hardware/software partitioning algorithm for digital signal processor cores with two types of register files

Togawa, N., Sakurai, T., Yanagisawa, M. & Ohtsuki, T., 2000, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. p. 544-547 4 p.

研究成果: Conference contribution

Digital signal processors
Hardware
Motion estimation
Wavelet transforms
Wavelets
High Performance
Wavelet Coefficients
6 引用 (Scopus)

An area/time optimizing algorithm in high-level synthesis for control-based hardwares

Togawa, N., Ienaga, M., Yanagisawa, M. & Ohtsuki, T., 2000, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 309-312 4 p.

研究成果: Conference contribution

Hardware
Application programs
Flow control
Flow graphs
Computer hardware
1 引用 (Scopus)

CAM processor synthesis based on behavioral descriptions

Togawa, N., Wakui, T., Yoden, T., Terajima, M., Yanagisawa, M. & Ohtsuki, T., 2000 12, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2464-2473 10 p.

研究成果: Article

Associative storage
Synthesis
Application programs
Unit
Memory Function
1999
1 引用 (Scopus)
Logic
Boolean Networks
Minimise
Table lookup
Look-up Table
16 引用 (Scopus)
Digital Signal Processor
Digital signal processors
Application programs
kernel
Computer hardware
Routing algorithms
Field programmable gate arrays (FPGA)
Electric power utilization
Networks (circuits)
Motion estimation
Image coding
Phase matching
Computational complexity
Data transfer
1998
Scheduling algorithms
Scheduling Algorithm
Fast Algorithm
Synthesis
Connectivity
Data flow graphs
High-level Synthesis
Flow Graphs
Digital signal processing
Data Flow
Table lookup
Look-up Table
Reconfiguration
Field Programmable Gate Array
System Design
1 引用 (Scopus)

High-level synthesis system for digital signal processing based on enumerating data-flow graphs

Togawa, N., Hisaki, T., Yanagisawa, M. & Ohtsuki, T., 1998, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE, p. 265-274 10 p.

研究成果: Chapter

Data flow graphs
Digital signal processing
Hardware
Computer hardware description languages
Scheduling
4 引用 (Scopus)

Incremental placement and global routing algorithm for field-programmable gate arrays

Togawa, N., Hagi, K., Yanagisawa, M. & Ohtsuki, T., 1998, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE, p. 519-526 8 p.

研究成果: Chapter

Routing algorithms
Field programmable gate arrays (FPGA)
Specifications
7 引用 (Scopus)
Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)
3 引用 (Scopus)

Simultaneous placement and global routing algorithm for FPGAs with power optimization

Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1998, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. Piscataway, NJ, United States: IEEE, p. 125-128 4 p.

研究成果: Chapter

Routing algorithms
Field programmable gate arrays (FPGA)
Electric power utilization
Networks (circuits)