年単位の研究成果
研究成果
2020
Scalable stochastic number duplicators for accuracy-flexible arithmetic circuit design
Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2020, ： : IPSJ Transactions on System LSI Design Methodology. 13, p. 10-20 11 p.研究成果: Article
公開
1
引用
（Scopus）
2018
A relaxed bit-write-reducing and error-correcting code for non-volatile memories
Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 7 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1045-1052 8 p.研究成果: Article
Stochastic number duplicators based on bit re-arrangement using randomized bit streams
Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 7 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1002-1013 12 p.研究成果: Article
5
引用
（Scopus）
2016
A bit-write-reducing and error-correcting code generation method by clustering ECC codewords for non-volatile memories
Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 12 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2398-2411 14 p.研究成果: Article
1
引用
（Scopus）
2015
Code generation limiting maximum and minimum hamming distances for non-volatile memories
Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2015 12 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2484-2493 10 p.研究成果: Article
2
引用
（Scopus）
ECC-Based bit-write reduction code generation for non-volatile memory
Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2015 12 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2494-2504 11 p.研究成果: Article
2
引用
（Scopus）
2013
A high-speed trace-driven cache configuration simulator for dual-core processor L1 caches
Tawada, M., Yanagisawa, M. & Togawa, N., 2013 6, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 6, p. 1283-1292 10 p.研究成果: Article
2011
Exact, fast and flexible L1 cache configuration simulation for embedded systems
Tawada, M., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011 12 5, ： : IPSJ Transactions on System LSI Design Methodology. 4, p. 166-181 16 p.研究成果: Article
Speeding-up exact and fast FIFO-based cache configuration simulation
Tawada, M., Yanagisawa, M. & Togawa, N., 2011 8 1, ： : ieice electronics express. 8, 14, p. 1161-1167 7 p.研究成果: Article
3
引用
（Scopus）