Masashi Tawada – 研究成果 — 早稲田大学

Scopus著者プロファイル

ウェブサイトhttps://w-rdb.waseda.jp/html/100001351_ja.html

年別の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

48 被引用数
4 h-index
20 Conference contribution
11 Article

11 件

フィルター

2021
Mapping induced subgraph isomorphism problems to ising models and its evaluations by an ising machine
Yoshimura, N., Tawada, M., Tanaka, S., Arai, J., Yagi, S., Uchiyama, H. & Togawa, N., 2021 4, In: IEICE Transactions on Information and Systems. E104.D, 4, p. 481-489 9 p.
研究成果: Article › 査読

Open Access
1 被引用数 (Scopus)
2020
How to Reduce the Bit-width of an Ising Model by Adding Auxiliary Spins
Oku, D., Tawada, M., Tanaka, S. & Togawa, N., 2020, (Accepted/In press) In: IEEE Transactions on Computers.
研究成果: Article › 査読

Open Access
1 被引用数 (Scopus)
Scalable stochastic number duplicators for accuracy-flexible arithmetic circuit design
Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2020, In: IPSJ Transactions on System LSI Design Methodology. 13, p. 10-20 11 p.
研究成果: Article › 査読

Open Access
1 被引用数 (Scopus)
2018
A relaxed bit-write-reducing and error-correcting code for non-volatile memories
Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 7, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1045-1052 8 p.
研究成果: Article › 査読
Stochastic number duplicators based on bit re-arrangement using randomized bit streams
Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 7 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1002-1013 12 p.
研究成果: Article › 査読
5 被引用数 (Scopus)
2016
A bit-write-reducing and error-correcting code generation method by clustering ECC codewords for non-volatile memories
Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 12 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2398-2411 14 p.
研究成果: Article › 査読
1 被引用数 (Scopus)
2015
Code generation limiting maximum and minimum hamming distances for non-volatile memories
Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2015 12 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2484-2493 10 p.
研究成果: Article › 査読
2 被引用数 (Scopus)
ECC-Based bit-write reduction code generation for non-volatile memory
Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2015 12, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2494-2504 11 p.
研究成果: Article › 査読
2 被引用数 (Scopus)
2013
A high-speed trace-driven cache configuration simulator for dual-core processor L1 caches
Tawada, M., Yanagisawa, M. & Togawa, N., 2013 6, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 6, p. 1283-1292 10 p.
研究成果: Article › 査読
2011
Exact, fast and flexible L1 cache configuration simulation for embedded systems
Tawada, M., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 166-181 16 p.
研究成果: Article › 査読
Speeding-up exact and fast FIFO-based cache configuration simulation
Tawada, M., Yanagisawa, M. & Togawa, N., 2011, In: ieice electronics express. 8, 14, p. 1161-1167 7 p.
研究成果: Article › 査読
3 被引用数 (Scopus)