• 933 引用
  • 15 h指数
1994 …2020

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

1994
12 引用 (Scopus)

Maple: a simultaneous technology mapping, placement, and global routing algorithm for FPGAs

Togawa, N., Sato, M. & Ohtsuki, T., 1994 12 1, p. 554-559. 6 p.

研究成果: Paper

Simultaneous placement and global routing algorithm for FPGAs

Togawa, N., Sato, M. & Ohtsuki, T., 1994 12 1, : : Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 483-486 4 p.

研究成果: Conference article

1 引用 (Scopus)
1995
2 引用 (Scopus)
1 引用 (Scopus)
1996
2 引用 (Scopus)
3 引用 (Scopus)
1997
3 引用 (Scopus)

Fast scheduling and allocation algorithms for entropy CODEC

Suzuki, K., Togawa, N., Sato, M. & Ohtsuki, T., 1997 1 1, : : IEICE Transactions on Information and Systems. E80-D, 10, p. 982-992 11 p.

研究成果: Article

5 引用 (Scopus)
1998
1 引用 (Scopus)

Incremental placement and global routing algorithm for field-programmable gate arrays

Togawa, N., Hagi, K., Yanagisawa, M. & Ohtsuki, T., 1998 12 1, p. 519-526. 8 p.

研究成果: Paper

4 引用 (Scopus)
7 引用 (Scopus)

Simultaneous placement and global routing algorithm for FPGAs with power optimization

Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1998 12 1, IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings. IEEE, p. 125-128 4 p. (IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings).

研究成果: Conference contribution

3 引用 (Scopus)
1999
1 引用 (Scopus)
16 引用 (Scopus)
2000
9 引用 (Scopus)
1 引用 (Scopus)

An area/time optimizing algorithm in high-level synthesis for control-based hardwares

Togawa, N., Ienaga, M., Yanagisawa, M. & Ohtsuki, T., 2000 12 1, Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000. p. 309-312 4 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

6 引用 (Scopus)

CAM processor synthesis based on behavioral descriptions

Togawa, N., Wakui, T., Yoden, T., Terajima, M., Yanagisawa, M. & Ohtsuki, T., 2000 12 1, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2464-2473 10 p.

研究成果: Article

1 引用 (Scopus)
2001
1 引用 (Scopus)

Area/delay estimation for digital signal processor cores

Miyaoka, Y., Kataoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2001 1 1, Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., p. 156-161 6 p. 913297. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 巻数 2001-January).

研究成果: Conference contribution

6 引用 (Scopus)
4 引用 (Scopus)
2002
3 引用 (Scopus)

An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions

Miyaoka, Y., Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Institute of Electrical and Electronics Engineers Inc., 巻 1. p. 171-176 6 p. 1114930

研究成果: Conference contribution

4 引用 (Scopus)

VLSI architecture for a flexible motion estimation with parameters

Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002, Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., p. 452-457 6 p. 994962

研究成果: Conference contribution

4 引用 (Scopus)
2003
2 引用 (Scopus)

A hardware/software partitioning algorithm for SIMD processor cores

Tachikake, K., Togawa, N., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 1 1, Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., p. 135-140 6 p. 1195006. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 巻数 2003-January).

研究成果: Conference contribution

2 引用 (Scopus)
2004

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 6 1, p. 250-255. 6 p.

研究成果: Paper

Alternative run-length coding through scan chain reconfiguration for joint minimization of test data volume and power consumption in scan test

Shi, Y., Kimura, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 12 1, Proceedings of the Asian Test Symposium, ATS'04. p. 432-437 6 p. (Proceedings of the Asian Test Symposium).

研究成果: Conference contribution

2 引用 (Scopus)

An efficient algorithm/architecture codesign for image encoders

Choi, J., Togawa, N., Ikenaga, T., Goto, S., Yanagisawa, M. & Ohtsuki, T., 2004 12 1, : : Midwest Symposium on Circuits and Systems. 2, p. II469-II472

研究成果: Conference article

1 引用 (Scopus)

A reconfigurable adaptive FEC system for reliable wireless communications

Shimizu, K., Togawa, N., Ikenaga, T., Yanagisawa, M., Goto, S. & Ohtsuki, T., 2004 12 1, p. 13-16. 4 p.

研究成果: Paper

4 引用 (Scopus)

A thread partitioning algorithm in low power high-level synthesis

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 6 1, p. 74-79. 6 p.

研究成果: Paper

4 引用 (Scopus)

Experimental evaluation of high-level energy optimization based on thread partitioning

Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 12 1, p. 161-164. 4 p.

研究成果: Paper

FPGA-based reconfigurable adaptive FEC

Shimizu, K., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 12, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3036-3046 11 p.

研究成果: Article

2 引用 (Scopus)

Instruction set and functional unit synthesis for SIMD processor cores

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2004 6 1, p. 743-750. 8 p.

研究成果: Paper

3 引用 (Scopus)