• 939 引用
  • 15 h指数
1994 …2020

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

2016

Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 7 29, ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 巻 2016-July. p. 978-981 4 p. 7527406

研究成果: Conference contribution

Small-sized and noise-reducing power analyzer design for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516927

研究成果: Conference contribution

2 引用 (Scopus)
2015

A bit-write reduction method based on error-correcting codes for non-volatile memories

Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2015 3 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 496-501 6 p. 7059055

研究成果: Conference contribution

5 引用 (Scopus)

A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Fujiwara, K., Abe, S., Kawamura, K., Yanagisawa, M. & Togawa, N., 2015 2 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February 版 Institute of Electrical and Electronics Engineers Inc., p. 244-247 4 p. 7032765. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 巻数 2015-February, 番号 February).

研究成果: Conference contribution

1 引用 (Scopus)

A floorplan-aware high-level synthesis technique with delay-variation tolerance

Kawamura, K., Hagio, Y., Shi, Y. & Togawa, N., 2015 9 30, Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., p. 122-125 4 p. 7285065

研究成果: Conference contribution

2 引用 (Scopus)
2 引用 (Scopus)

A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration

Terada, K., Yanagisawa, M. & Togawa, N., 2015 7 27, Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 巻 2015-July. p. 2129-2132 4 p. 7169100

研究成果: Conference contribution

1 引用 (Scopus)

A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration

Teradat, K., Yanagisawa, M. & Togawa, N., 2015 2 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February 版 Institute of Electrical and Electronics Engineers Inc., p. 248-251 4 p. 7032766. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 巻数 2015-February, 番号 February).

研究成果: Conference contribution

1 引用 (Scopus)
5 引用 (Scopus)
1 引用 (Scopus)

An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction

Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 2 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February 版 Institute of Electrical and Electronics Engineers Inc., p. 300-303 4 p. 7032779. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 巻数 2015-February, 番号 February).

研究成果: Conference contribution

1 引用 (Scopus)
3 引用 (Scopus)
1 引用 (Scopus)

A score-based classification method for identifying Hardware-Trojans at gate-level netlists

Oya, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 4 22, Proceedings -Design, Automation and Test in Europe, DATE. Institute of Electrical and Electronics Engineers Inc., 巻 2015-April. p. 465-470 6 p. 7092434

研究成果: Conference contribution

50 引用 (Scopus)

A write-reducing and error-correcting code generation method for non-volatile memories

Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2015 2 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February 版 Institute of Electrical and Electronics Engineers Inc., p. 304-307 4 p. 7032780. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 巻数 2015-February, 番号 February).

研究成果: Conference contribution

3 引用 (Scopus)
2 引用 (Scopus)
2 引用 (Scopus)

Fast source optimization by clustering algorithm based on lithography properties

Tawada, M., Hashimoto, T., Sakanushi, K., Nojima, S., Kotani, T., Yanagisawa, M. & Togawa, N., 2015, Proceedings of SPIE - The International Society for Optical Engineering. SPIE, 巻 9427. 94270K

研究成果: Conference contribution

In-situ timing monitoring methods for variation-resilient designs

Shi, Y. & Togawa, N., 2015 2 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February 版 Institute of Electrical and Electronics Engineers Inc., p. 735-738 4 p. 7032886. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 巻数 2015-February, 番号 February).

研究成果: Conference contribution

Scan-based side-channel attack against symmetric key ciphers using scan signatures

Fujishiro, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 9 30, Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., p. 309-312 4 p. 7285112

研究成果: Conference contribution

1 引用 (Scopus)

Scan-based side-channel attack on Camellia cipher using scan signatures

Hang, H., Fujishiro, M., Kodera, H., Yanagisawa, M. & Togawa, N., 2015 2 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February 版 Institute of Electrical and Electronics Engineers Inc., p. 252-255 4 p. 7032767. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 巻数 2015-February, 番号 February).

研究成果: Conference contribution

3 引用 (Scopus)
1 引用 (Scopus)

Secure scan design using improved random order and its evaluations

Oya, M., Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 2 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February 版 Institute of Electrical and Electronics Engineers Inc., p. 555-558 4 p. 7032842. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 巻数 2015-February, 番号 February).

研究成果: Conference contribution

4 引用 (Scopus)
2014
5 引用 (Scopus)

Foreword: Special section on VLSI design and CAD algorithms

Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T. および17人, Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S. I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M. & Watanabe, T., 2014 12 1, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, 1 p.

研究成果: Editorial

Linear and bi-linear interpolation circuits using selector logics and their evaluations

Shio, M., Yanagisawa, M. & Togawa, N., 2014 1 1, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., p. 1436-1439 4 p. 6865415. (Proceedings - IEEE International Symposium on Circuits and Systems).

研究成果: Conference contribution

7 引用 (Scopus)
5 引用 (Scopus)

Scan-based attack on the LED block cipher using scan signatures

Fujishiro, M., Yanagisawa, M. & Togawa, N., 2014 1 1, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., p. 1460-1463 4 p. 6865421. (Proceedings - IEEE International Symposium on Circuits and Systems).

研究成果: Conference contribution

3 引用 (Scopus)
3 引用 (Scopus)

Throughput driven check point selection in suspicious timing error prediction based designs

Igarashi, H., Shi, Y., Yanagisawa, M. & Togawa, N., 2014 1 1, 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings. IEEE Computer Society, 6820280. (2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings).

研究成果: Conference contribution

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2013 8 15, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533808. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

研究成果: Conference contribution

A partial redundant fault-secure high-level synthesis algorithm for RDR architectures

Kawamura, K., Tanaka, S., Yanagisawa, M. & Togawa, N., 2013 9 9, 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013. p. 1736-1739 4 p. 6572200. (Proceedings - IEEE International Symposium on Circuits and Systems).

研究成果: Conference contribution

1 引用 (Scopus)

Concurrent faulty clock detection for crypto circuits against clock glitch based DFA

Igarashi, H., Shi, Y., Yanagisawa, M. & Togawa, N., 2013 9 9, 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013. p. 1432-1435 4 p. 6572125. (Proceedings - IEEE International Symposium on Circuits and Systems).

研究成果: Conference contribution

2 引用 (Scopus)

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Matsuno, S., Tawada, M., Yanagisawa, M., Kimura, S., Togawa, N. & Sugibayashi, T., 2013 1 1, 2013 IEEE 10th International Conference on ASIC, ASICON 2013. IEEE Computer Society, 6811826. (Proceedings of International Conference on ASIC).

研究成果: Conference contribution

1 引用 (Scopus)
2 引用 (Scopus)

High-level synthesis with post-silicon delay tuning for RDR architectures

Hagio, Y., Yanagisawa, M. & Togawa, N., 2013 1 1, ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, p. 194-197 4 p. 6863970. (ISOCC 2013 - 2013 International SoC Design Conference).

研究成果: Conference contribution

2 引用 (Scopus)
2 引用 (Scopus)

Scan-based attack against Trivium stream cipher independent of scan structure

Fujishiro, M., Yanagisawa, M. & Togawa, N., 2013 1 1, 2013 IEEE 10th International Conference on ASIC, ASICON 2013. IEEE Computer Society, 6811855. (Proceedings of International Conference on ASIC).

研究成果: Conference contribution

2 引用 (Scopus)

Secure scan design with dynamically configurable connection

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2013 1 1, Proceedings - 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing, PRDC 2013. IEEE Computer Society, p. 256-262 7 p. 6820873. (Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC).

研究成果: Conference contribution

16 引用 (Scopus)

Suspicious timing error prediction with in-cycle clock gating

Shi, Y., Igarashi, H., Togawa, N. & Yanagisawa, M., 2013 7 5, Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013. p. 335-340 6 p. 6523631. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

研究成果: Conference contribution

16 引用 (Scopus)
2012

A hybrid NoC architecture utilizing packet transmission priority control method

Lee, S., Togawa, N., Sekihara, Y., Aoki, T. & Onozawa, A., 2012 12 1, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 404-407 4 p. 6419057. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

研究成果: Conference contribution

4 引用 (Scopus)
1 引用 (Scopus)
8 引用 (Scopus)

A novel BMNoC configuration algorithm utilizing communication volume and locality among cores

Lee, S., Togawa, N., Aoki, T. & Onozawa, A., 2012 9 28, p. 1668-1671. 4 p.

研究成果: Paper

Dynamically changeable secure scan architecture against scan-based side channel attack

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2012 12 1, ISOCC 2012 - 2012 International SoC Design Conference. p. 155-158 4 p. 6407063. (ISOCC 2012 - 2012 International SoC Design Conference).

研究成果: Conference contribution

26 引用 (Scopus)
13 引用 (Scopus)