• 933 引用
  • 15 h指数
1994 …2020

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

2012

Energy-efficient high-level synthesis for HDR architectures with clock gating

Akasaka, H., Yanagisawa, M. & Togawa, N., 2012 12 1, ISOCC 2012 - 2012 International SoC Design Conference. p. 135-138 4 p. 6407058. (ISOCC 2012 - 2012 International SoC Design Conference).

研究成果: Conference contribution

2 引用 (Scopus)
14 引用 (Scopus)

Scan-based attack against des cryptosystems using scan signatures

Kodera, H., Yanagisawa, M. & Togawa, N., 2012 12 1, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 599-602 4 p. 6419106. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

研究成果: Conference contribution

15 引用 (Scopus)

State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2012 12 1, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 607-610 4 p. 6419108. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

研究成果: Conference contribution

7 引用 (Scopus)

Weighted adders with selector logics for super-resolution and its FPGA-based evaluation

Yoshihara, H., Yanagisawa, M. & Togawa, N., 2012 12 1, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012. p. 603-606 4 p. 6419107. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

研究成果: Conference contribution

1 引用 (Scopus)
2011
1 引用 (Scopus)
12 引用 (Scopus)

Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies

Tawada, M., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011 6 28, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 247-250 4 p. 5783622. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

研究成果: Conference contribution

4 引用 (Scopus)
3 引用 (Scopus)

Scan vulnerability in elliptic curve cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2011 12 5, : : IPSJ Transactions on System LSI Design Methodology. 4, p. 47-59 13 p.

研究成果: Article

6 引用 (Scopus)
3 引用 (Scopus)
2010

A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit

Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 12 1, Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. p. 1083-1086 4 p. 5774956. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

研究成果: Conference contribution

BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers

Lee, S. J., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 12 1, Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. p. 712-715 4 p. 5774825. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

研究成果: Conference contribution

3 引用 (Scopus)

Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 8 31, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. p. 921-924 4 p. 5537401. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

研究成果: Conference contribution

4 引用 (Scopus)

Scan-based attack against elliptic curve cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 4 28, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 407-412 6 p. 5419848. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

48 引用 (Scopus)
48 引用 (Scopus)

State-dependent changeable scan architecture against scan-based side channel attacks

Nara, R., Atobe, H., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 8 31, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. p. 1867-1870 4 p. 5537859. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

研究成果: Conference contribution

9 引用 (Scopus)

VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding

Shi, Y., Tokumitsu, K., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 12 1, Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. p. 1139-1142 4 p. 5774925. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

研究成果: Conference contribution

1 引用 (Scopus)
2009
32 引用 (Scopus)

Design-for-secure-test for crypto cores

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12 15, International Test Conference, ITC 2009 - Proceedings. 5355900. (Proceedings - International Test Conference).

研究成果: Conference contribution

7 引用 (Scopus)

Exact and fast L1 cache simulation for embedded systems

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 4 20, Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009. p. 817-822 6 p. 4796581. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

25 引用 (Scopus)
8 引用 (Scopus)
2008
3 引用 (Scopus)

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

Nagashima, A., Imai, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 12 1, Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems. p. 705-708 4 p. 4746121. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

研究成果: Conference contribution

1 引用 (Scopus)

FIR filter design on flexible engine/generic ALU array and its dedicated synthesis algorithm

Tamura, R., Honma, M., Togawa, N., Yanagisawa, M., Ohtsuki, T. & Satoh, M., 2008 12 1, Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems. p. 701-704 4 p. 4746120. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

研究成果: Conference contribution

4 引用 (Scopus)
8 引用 (Scopus)

GECOM: Test data compression combined with all unknown response masking

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 8 21, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 577-582 6 p. 4484018. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

5 引用 (Scopus)

High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 9 5, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. p. 164-167 4 p. 4542438. (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT).

研究成果: Conference contribution

9 引用 (Scopus)

Scalable unified dual-radix architecture for Montgomery multiplication in GF{P) and GF(2n)

Tanimura, K., Nara, R., Kohara, S., Shimizu, K., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 8 21, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 697-702 6 p. 4484041. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

4 引用 (Scopus)

Unknown response masking with minimized observable response loss and mask data

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 12 1, Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems. p. 1779-1781 3 p. 4746386. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

研究成果: Conference contribution

2007
3 引用 (Scopus)

Power-efficient LDPC code decoder architecture

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2007 12 17, ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design. p. 359-362 4 p. (Proceedings of the International Symposium on Low Power Electronics and Design).

研究成果: Conference contribution

3 引用 (Scopus)
2006

A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006 1 1, : : IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.

研究成果: Article

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

Kohara, S., Tomono, N., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006 9 19, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. p. 594-599 6 p. 1594750. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 巻数 2006).

研究成果: Conference contribution

1 引用 (Scopus)

A parallel LSI architecture for LDPC decoder improving message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 12 1, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. p. 5099-5102 4 p. 1693779. (Proceedings - IEEE International Symposium on Circuits and Systems).

研究成果: Conference contribution

7 引用 (Scopus)

FCSCAN: An efficient multiscan-based test compression technique for test cost reduction

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2006 9 19, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. p. 653-658 6 p. 1594760. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 巻数 2006).

研究成果: Conference contribution

15 引用 (Scopus)

Memory-efficient accelerating schedule for LDPC decoder

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2006 12 1, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. p. 1317-1320 4 p. 4145643. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

研究成果: Conference contribution

9 引用 (Scopus)
5 引用 (Scopus)