• 856 引用
  • 14 h指数
1994 …2020
Pureに変更を加えた場合、すぐここに表示されます。

研究成果 1994 2020

2011
6 引用 (Scopus)
Cryptography
Networks (circuits)
Public key cryptography
Monitoring
Testing
3 引用 (Scopus)
configurations
Embedded systems
simulation
Simulators
central processing units
2010

A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit

Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 1083-1086 4 p. 5774956

研究成果: Conference contribution

Fast Fourier transforms
3 引用 (Scopus)

BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers

Lee, S., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 712-715 4 p. 5774825

研究成果: Conference contribution

Routers
Scalability
Communication
Network-on-chip
4 引用 (Scopus)

Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. p. 921-924 4 p. 5537401

研究成果: Conference contribution

Controllers
Scheduling
High level synthesis
46 引用 (Scopus)

Scan-based attack against elliptic curve cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 407-412 6 p. 5419848

研究成果: Conference contribution

Cryptography
Networks (circuits)
Public key cryptography
Monitoring
47 引用 (Scopus)
RSA Cryptosystem
Side Channel Attacks
Cryptography
Signature
Networks (circuits)
8 引用 (Scopus)

State-dependent changeable scan architecture against scan-based side channel attacks

Nara, R., Atobe, H., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. p. 1867-1870 4 p. 5537859

研究成果: Conference contribution

Flip flop circuits
Statistical methods
Hardware
Networks (circuits)
Side channel attack
1 引用 (Scopus)

VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding

Shi, Y., Tokumitsu, K., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 1139-1142 4 p. 5774925

研究成果: Conference contribution

Hardware
High definition television
Particle accelerators
Electric power utilization
Pixels
2009
Design Space Exploration
Cache
Data storage equipment
Embedded systems
Configuration
30 引用 (Scopus)
Discriminators
Cryptosystem
Cryptography
Attack
Networks (circuits)
Design Space Exploration
Cache
Data storage equipment
Embedded systems
Energy utilization
7 引用 (Scopus)

Design-for-secure-test for crypto cores

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12 15, Proceedings - International Test Conference. 5355900

研究成果: Conference contribution

Flip flop circuits
Flip
Design
25 引用 (Scopus)

Exact and fast L1 cache simulation for embedded systems

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 817-822 6 p. 4796581

研究成果: Conference contribution

Embedded systems
Data storage equipment
8 引用 (Scopus)
High-level Synthesis
Controllers
Floorplanning
Networks (circuits)
Controller
Montgomery multiplication
Cryptography
Multiplier
Clocks
Time delay
2008
3 引用 (Scopus)
Cryptography
Failure analysis
Testing
1 引用 (Scopus)

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

Nagashima, A., Imai, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 705-708 4 p. 4746121

研究成果: Conference contribution

Reconfigurable architectures
Decoding
Throughput
HIgh speed networks
Mobile devices
4 引用 (Scopus)

FIR filter design on flexible engine/generic ALU array and its dedicated synthesis algorithm

Tamura, R., Honma, M., Togawa, N., Yanagisawa, M., Ohtsuki, T. & Satoh, M., 2008, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 701-704 4 p. 4746120

研究成果: Conference contribution

FIR filters
Engines
Digital storage
Specifications
Processing
8 引用 (Scopus)
Scheduling
Networks (circuits)
High level synthesis
5 引用 (Scopus)

GECOM: Test data compression combined with all unknown response masking

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 577-582 6 p. 4484018

研究成果: Conference contribution

Data compression
Networks (circuits)
Cost reduction
Product design
Masks
9 引用 (Scopus)

High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. p. 164-167 4 p. 4542438

研究成果: Conference contribution

Scheduling
Networks (circuits)
High level synthesis
LDPC Codes
Dissipation
Energy dissipation
Compression
Clocks
4 引用 (Scopus)

Scalable unified dual-radix architecture for Montgomery multiplication in GF{P) and GF(2n)

Tanimura, K., Nara, R., Kohara, S., Shimizu, K., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 697-702 6 p. 4484041

研究成果: Conference contribution

Cryptography
Clocks
Time delay
Public key cryptography
Parallel architectures

Unknown response masking with minimized observable response loss and mask data

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 1779-1781 3 p. 4746386

研究成果: Conference contribution

Masks
Degradation
2007
3 引用 (Scopus)

Design for secure test - A case study on pipelined advanced encryption standard

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2007, Proceedings - IEEE International Symposium on Circuits and Systems. p. 149-152 4 p. 4252593

研究成果: Conference contribution

Cryptography
Hardware
Testing
Security of data
Data communication systems
3 引用 (Scopus)

Power-efficient LDPC code decoder architecture

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2007, Proceedings of the International Symposium on Low Power Electronics and Design. p. 359-362 4 p.

研究成果: Conference contribution

Decoding
Energy dissipation
Throughput
Shift registers
Clocks
2006
Cryptography
Hardware
1 引用 (Scopus)

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

Kohara, S., Tomono, N., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 巻 2006. p. 594-599 6 p. 1594750

研究成果: Conference contribution

Hardware
Networks (circuits)
Communication
Specifications
System-on-chip
7 引用 (Scopus)

A parallel LSI architecture for LDPC decoder improving message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006, Proceedings - IEEE International Symposium on Circuits and Systems. p. 5099-5102 4 p. 1693779

研究成果: Conference contribution

Message passing
Hardware
Iterative decoding
Decoding
Throughput
14 引用 (Scopus)

FCSCAN: An efficient multiscan-based test compression technique for test cost reduction

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 巻 2006. p. 653-658 6 p. 1594760

研究成果: Conference contribution

Cost reduction
Fans
Data compression
Product design
Costs

Memory-efficient accelerating schedule for LDPC decoder

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2006, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. p. 1317-1320 4 p. 4145643

研究成果: Conference contribution

Message passing
Data storage equipment
9 引用 (Scopus)
Message passing
Message Passing
High Efficiency
Iterative decoding
Schedule
5 引用 (Scopus)
Message passing
Message Passing
Schedule
Static random access storage
Energy dissipation
2 引用 (Scopus)
Data compression
Data Compression
Coding
Networks (circuits)
Encoding

Special section on VLSI Design and CAD Algorithms

Onodera, H., Ikeda, M., Ishihara, T., Isshiki, T., Inoue, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kuga, M., Kurokawa, A., Sato, T., Shibuya, T., Shiraishi, Y., Takagi, K., Takahashi, A., Takeuchi, Y., Togawa, N., Tomiyama, H. および10人, Nakamura, Y., Hamaguchi, K., Miura, Y., Minato, S. I., Yamaguchi, R., Yamada, M., Yuminaka, Y., Watanabe, T., Hashimoto, M. & Miyazaki, M., 2006 12, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3377 1 p.

研究成果: Article

VLSI Design
Computer aided design
2005

A processor core synthesis system in IP-based SoC design

Tomono, N., Kohara, S., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 巻 1. p. 286-291 6 p. 1466175

研究成果: Conference contribution

Hardware
System-on-chip
1 引用 (Scopus)
Decomposition
17 引用 (Scopus)

Low power test compression technique for designs with multiple scan chains

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings of the Asian Test Symposium. 巻 2005. p. 386-389 4 p. 1575460

研究成果: Conference contribution

Electric power utilization
Discrete Fourier transforms
Hardware
26 引用 (Scopus)

Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2005, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. 巻 2005. p. 503-510 8 p. 1524200

研究成果: Conference contribution

Message passing
Decoding
Field programmable gate arrays (FPGA)
Pipelines
Hardware
3 引用 (Scopus)
Reed-Solomon codes
Adaptive systems
Error correction
Hardware
Communication channels (information theory)

Reconfigurable adaptive FEC system with interleaving

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2005, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 巻 2. p. 1252-1255 4 p. 1466570

研究成果: Conference contribution

Adaptive systems
Hardware
Error correction
Throughput
Parallelism
Synthesis
Unit
Optimization
Timing

Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations

Togawa, N., Kawazu, H., Uchida, J., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005, Proceedings - IEEE International Symposium on Circuits and Systems. p. 3499-3502 4 p. 1465383

研究成果: Conference contribution

Hardware
2004

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 250-255 6 p.

研究成果: Conference contribution

Application programs
Data storage equipment
Hardware
Hardware
Software
Unit
Application programs
Cycle
2 引用 (Scopus)
Coloring
Heuristic algorithms
Electric power utilization
System-on-chip