• 939 引用
  • 15 h指数
1994 …2020

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

2015

A write-reducing and error-correcting code generation method for non-volatile memories

Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2015 2 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February 版 Institute of Electrical and Electronics Engineers Inc., p. 304-307 4 p. 7032780. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 巻数 2015-February, 番号 February).

研究成果: Conference contribution

3 引用 (Scopus)
2 引用 (Scopus)
2 引用 (Scopus)

Fast source optimization by clustering algorithm based on lithography properties

Tawada, M., Hashimoto, T., Sakanushi, K., Nojima, S., Kotani, T., Yanagisawa, M. & Togawa, N., 2015, Proceedings of SPIE - The International Society for Optical Engineering. SPIE, 巻 9427. 94270K

研究成果: Conference contribution

In-situ timing monitoring methods for variation-resilient designs

Shi, Y. & Togawa, N., 2015 2 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February 版 Institute of Electrical and Electronics Engineers Inc., p. 735-738 4 p. 7032886. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 巻数 2015-February, 番号 February).

研究成果: Conference contribution

Scan-based side-channel attack against symmetric key ciphers using scan signatures

Fujishiro, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 9 30, Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., p. 309-312 4 p. 7285112

研究成果: Conference contribution

1 引用 (Scopus)

Scan-based side-channel attack on Camellia cipher using scan signatures

Hang, H., Fujishiro, M., Kodera, H., Yanagisawa, M. & Togawa, N., 2015 2 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February 版 Institute of Electrical and Electronics Engineers Inc., p. 252-255 4 p. 7032767. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 巻数 2015-February, 番号 February).

研究成果: Conference contribution

3 引用 (Scopus)
1 引用 (Scopus)

Secure scan design using improved random order and its evaluations

Oya, M., Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2015 2 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February 版 Institute of Electrical and Electronics Engineers Inc., p. 555-558 4 p. 7032842. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 巻数 2015-February, 番号 February).

研究成果: Conference contribution

4 引用 (Scopus)
2016
1 引用 (Scopus)

A delay variation and floorplan aware high-level synthesis algorithm with body biasing

Igawa, K., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 5 25, Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. IEEE Computer Society, 巻 2016-May. p. 75-80 6 p. 7479179

研究成果: Conference contribution

1 引用 (Scopus)

A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 5 31, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 7482547

研究成果: Conference contribution

3 引用 (Scopus)
1 引用 (Scopus)

A high-performance circuit design algorithm using data dependent approximation

Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 12 27, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., p. 95-96 2 p. 7799750

研究成果: Conference contribution

A landmark-based route recommendation method for pedestrian walking strategies

Bao, S., Nitta, T., Shindou, D., Yanagisawa, M. & Togawa, N., 2016 2 3, 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015. Institute of Electrical and Electronics Engineers Inc., p. 672-673 2 p. 7398511

研究成果: Conference contribution

3 引用 (Scopus)

A low-power soft error tolerant latch scheme

Tajima, S., Shi, Y., Togawa, N. & Yanagisawa, M., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516885

研究成果: Conference contribution

1 引用 (Scopus)

A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures

Igawa, K., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 2 12, Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015. Buchner, T., Zhao, D., Bhatia, K. & Sridhar, R. (版). IEEE Computer Society, p. 7-12 6 p. 7406898. (International System on Chip Conference; 巻数 2016-February).

研究成果: Conference contribution

2 引用 (Scopus)

A safe and comprehensive route finding method for pedestrian based on lighting and landmark

Bao, S., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 12 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800525

研究成果: Conference contribution

3 引用 (Scopus)

A visible corner-landmark based route finding algorithm for pedestrian navigation

Takeda, K., Nitta, T., Shindou, D., Yanagisawa, M. & Togawa, N., 2016 2 3, 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015. Institute of Electrical and Electronics Engineers Inc., p. 601-602 2 p. 7398498

研究成果: Conference contribution

2 引用 (Scopus)
1 引用 (Scopus)

Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories

Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 1 5, 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., p. 682-689 8 p. 7372636

研究成果: Conference contribution

2 引用 (Scopus)

Clock skew estimate modeling for FPGA high-level synthesis and its application

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516905

研究成果: Conference contribution

3 引用 (Scopus)

Comprehensive deformed map generation for wristwatch-type wearable devices based on landmark-based partitioning

Kono, K., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 12 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800432

研究成果: Conference contribution

2 引用 (Scopus)

Effective parallel algorithm for GPGPU-accelerated explicit routing optimization

Kikuta, K., Oki, E., Yamanaka, N., Togawa, N. & Nakazato, H., 2016 2 23, 2015 IEEE Global Communications Conference, GLOBECOM 2015. Institute of Electrical and Electronics Engineers Inc., 7416979

研究成果: Conference contribution

1 引用 (Scopus)

Hardware Trojans classification for gate-level netlists based on machine learning

Hasegawa, K., Oya, M., Yanagisawa, M. & Togawa, N., 2016 10 20, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016. Institute of Electrical and Electronics Engineers Inc., p. 203-206 4 p. 7604700

研究成果: Conference contribution

30 引用 (Scopus)
7 引用 (Scopus)

Hash-Table and balanced-Tree based fib architecture for ccn routers

Shimazaki, K., Aoki, T., Hatano, T., Otsuka, T., Miyazaki, A., Tsuda, T. & Togawa, N., 2016 12 27, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., p. 67-68 2 p. 7799736

研究成果: Conference contribution

1 引用 (Scopus)

Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation

Igarashi, K., Yanagisawa, M. & Togawa, N., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7517027

研究成果: Conference contribution

2 引用 (Scopus)

Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation

Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516962

研究成果: Conference contribution

In-situ Trojan authentication for invalidating hardware-Trojan functions

Oya, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 5 25, Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. IEEE Computer Society, 巻 2016-May. p. 152-157 6 p. 7479192

研究成果: Conference contribution

4 引用 (Scopus)

Partitioning-based multiplexer network synthesis for field-data extractors

Ito, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2016 2 12, Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015. Buchner, T., Zhao, D., Bhatia, K. & Sridhar, R. (版). IEEE Computer Society, p. 263-268 6 p. 7406960. (International System on Chip Conference; 巻数 2016-February).

研究成果: Conference contribution

3 引用 (Scopus)

Pedestrian navigation based on landmark recognition using glass-type wearable devices

Yano, R., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 12 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800433

研究成果: Conference contribution

Redesign for untrusted gate-level netlists

Oya, M., Yanagisawa, M. & Togawa, N., 2016 10 20, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016. Institute of Electrical and Electronics Engineers Inc., p. 219-220 2 p. 7604706

研究成果: Conference contribution

Rotator-based multiplexer network synthesis for field-data extractors

Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2016 7 2, Proceedings - 29th IEEE International System on Chip Conference, SOCC 2016. Bhatia, K., Alioto, M., Zhao, D., Marshall, A. & Sridhar, R. (版). IEEE Computer Society, p. 194-199 6 p. 7905464. (International System on Chip Conference; 巻数 0).

研究成果: Conference contribution

1 引用 (Scopus)

Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 7 29, ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 巻 2016-July. p. 978-981 4 p. 7527406

研究成果: Conference contribution

Small-sized and noise-reducing power analyzer design for low-power IoT devices

Kitayama, R., Takenaka, T., Yanagisawa, M. & Togawa, N., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516927

研究成果: Conference contribution

2 引用 (Scopus)
2017
11 引用 (Scopus)

An accurate indoor positioning algorithm using particle filter based on the proximity of bluetooth beacons

Momose, R., Nitta, T., Yanagisawa, M. & Togawa, N., 2017 12 19, 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017. Institute of Electrical and Electronics Engineers Inc., 巻 2017-January. p. 1-5 5 p.

研究成果: Conference contribution

8 引用 (Scopus)

A robust scan-based side-channel attack method against HMAC-SHA-256 circuits

Oku, D., Yanagisawa, M. & Togawa, N., 2017 12 14, 2017 IEEE 7th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2017. IEEE Computer Society, 巻 2017-September. p. 79-84 6 p.

研究成果: Conference contribution

1 引用 (Scopus)
1 引用 (Scopus)

A stayed location estimation method for sparse GPS positioning information

Iwata, S., Nitta, T., Takayama, T., Yanagisawa, M. & Togawa, N., 2017 12 19, 2017 IEEE 6th Global Conference on Consumer Electronics, GCCE 2017. Institute of Electrical and Electronics Engineers Inc., 巻 2017-January. p. 1-5 5 p.

研究成果: Conference contribution

1 引用 (Scopus)

Effective write-reduction method for MLC non-volatile memory

Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2017 9 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050699

研究成果: Conference contribution

Hardware Trojan detection and classification based on steady state learning

Oya, M., Yanagisawa, M. & Togawa, N., 2017 9 19, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., p. 215-220 6 p. 8046225

研究成果: Conference contribution

1 引用 (Scopus)

Hardware Trojans classification for gate-level netlists using multi-layer neural networks

Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 9 19, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., p. 227-232 6 p. 8046227

研究成果: Conference contribution

26 引用 (Scopus)