• 939 引用
  • 15 h指数
1994 …2020

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

Conference contribution

A write-reducing and error-correcting code generation method for non-volatile memories

Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2015 2 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February 版 Institute of Electrical and Electronics Engineers Inc., p. 304-307 4 p. 7032780. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 巻数 2015-February, 番号 February).

研究成果: Conference contribution

3 引用 (Scopus)

Bicycle behavior recognition using sensors equipped with smartphone

Usami, Y., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2018 12 13, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2018. IEEE Computer Society, 巻 2018-September. 8576254

研究成果: Conference contribution

Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories

Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 1 5, 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., p. 682-689 8 p. 7372636

研究成果: Conference contribution

2 引用 (Scopus)

BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers

Lee, S. J., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 12 1, Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010. p. 712-715 4 p. 5774825. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

研究成果: Conference contribution

3 引用 (Scopus)

Capacitance Measurement of Running Hardware Devices and its Application to Malicious Modification Detection

Nishizawa, M., Hasegawa, K. & Togawa, N., 2019 1 8, 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc., p. 362-365 4 p. 8605668. (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018).

研究成果: Conference contribution

Clock skew estimate modeling for FPGA high-level synthesis and its application

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516905

研究成果: Conference contribution

3 引用 (Scopus)

Comprehensive deformed map generation for wristwatch-type wearable devices based on landmark-based partitioning

Kono, K., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2016 12 27, 2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016. Institute of Electrical and Electronics Engineers Inc., 7800432

研究成果: Conference contribution

2 引用 (Scopus)

Concurrent faulty clock detection for crypto circuits against clock glitch based DFA

Igarashi, H., Shi, Y., Yanagisawa, M. & Togawa, N., 2013 9 9, 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013. p. 1432-1435 4 p. 6572125. (Proceedings - IEEE International Symposium on Circuits and Systems).

研究成果: Conference contribution

2 引用 (Scopus)

Design-for-secure-test for crypto cores

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12 15, International Test Conference, ITC 2009 - Proceedings. 5355900. (Proceedings - International Test Conference).

研究成果: Conference contribution

7 引用 (Scopus)

Designing hardware trojans and their detection based on a SVM-based approach

Inoue, T., Hasegawa, K., Yanagisawa, M. & Togawa, N., 2018 1 8, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. IEEE Computer Society, 巻 2017-October. p. 811-814 4 p.

研究成果: Conference contribution

9 引用 (Scopus)

Designing subspecies of hardware trojans and their detection using neural network approach

Inoue, T., Hasegawa, K., Kobayashi, Y., Yanagisawa, M. & Togawa, N., 2018 12 13, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin, ICCE-Berlin 2018. IEEE Computer Society, 巻 2018-September. 8576247

研究成果: Conference contribution

1 引用 (Scopus)

Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis

Hasegawa, K., Yanagisawa, M. & Togawa, N., 2018 9 26, 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018. Maniatakos, M., Alexandrescu, D., Gizopoulos, D. & Papavramidou, P. (版). Institute of Electrical and Electronics Engineers Inc., p. 97-102 6 p. 8474113

研究成果: Conference contribution

2 引用 (Scopus)

Document-level sentiment classification in japanese by stem-based segmentation with category and data-source information

Bao, S. & Togawa, N., 2020 2, Proceedings - 14th IEEE International Conference on Semantic Computing, ICSC 2020. Institute of Electrical and Electronics Engineers Inc., p. 311-314 4 p. 9031471. (Proceedings - 14th IEEE International Conference on Semantic Computing, ICSC 2020).

研究成果: Conference contribution

Dynamically changeable secure scan architecture against scan-based side channel attack

Atobe, Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2012 12 1, ISOCC 2012 - 2012 International SoC Design Conference. p. 155-158 4 p. 6407063. (ISOCC 2012 - 2012 International SoC Design Conference).

研究成果: Conference contribution

26 引用 (Scopus)

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

Nagashima, A., Imai, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 12 1, Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems. p. 705-708 4 p. 4746121. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

研究成果: Conference contribution

1 引用 (Scopus)

Effectively Partitioned Implementation for Successive-Cancellation Polar Decoder

Ideguchi, Y., Kamiya, N., Tawada, M. & Togawa, N., 2019 8, 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, MWSCAS 2019. Institute of Electrical and Electronics Engineers Inc., p. 981-984 4 p. 8885174. (Midwest Symposium on Circuits and Systems; 巻数 2019-August).

研究成果: Conference contribution

Effective parallel algorithm for GPGPU-accelerated explicit routing optimization

Kikuta, K., Oki, E., Yamanaka, N., Togawa, N. & Nakazato, H., 2016 2 23, 2015 IEEE Global Communications Conference, GLOBECOM 2015. Institute of Electrical and Electronics Engineers Inc., 7416979

研究成果: Conference contribution

1 引用 (Scopus)

Effective write-reduction method for MLC non-volatile memory

Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2017 9 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050699

研究成果: Conference contribution

Efficient ising model mapping for induced subgraph isomorphism problems using ising machines

Yoshimura, N., Tawada, M., Tanaka, S., Arai, J., Yagi, S., Uchiyama, H. & Togawa, N., 2019 9, Proceedings - 2019 IEEE 9th International Conference on Consumer Electronics, ICCE-Berlin 2019. Velikic, G. & Gross, C. (版). IEEE Computer Society, p. 227-232 6 p. 8966218. (IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin; 巻数 2019-September).

研究成果: Conference contribution

Efficient Ising Model Mapping to Solving Slot Placement Problem

Kanamaru, S., Oku, D., Tawada, M., Tanaka, S., Hayashi, M., Yamaoka, M., Yanagisawa, M. & Togawa, N., 2019 3 6, 2019 IEEE International Conference on Consumer Electronics, ICCE 2019. Institute of Electrical and Electronics Engineers Inc., 8661947. (2019 IEEE International Conference on Consumer Electronics, ICCE 2019).

研究成果: Conference contribution

3 引用 (Scopus)

Empirical Evaluation on Anomaly Behavior Detection for Low-Cost Micro-Controllers Utilizing Accurate Power Analysis

Hasegawa, K., Chikamatsu, K. & Togawa, N., 2019 7, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019. Gizopoulos, D., Alexandrescu, D., Papavramidou, P. & Maniatakos, M. (版). Institute of Electrical and Electronics Engineers Inc., p. 54-57 4 p. 8854456. (2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019).

研究成果: Conference contribution

Energy-efficient high-level synthesis for HDR architectures with clock gating

Akasaka, H., Yanagisawa, M. & Togawa, N., 2012 12 1, ISOCC 2012 - 2012 International SoC Design Conference. p. 135-138 4 p. 6407058. (ISOCC 2012 - 2012 International SoC Design Conference).

研究成果: Conference contribution

2 引用 (Scopus)

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Matsuno, S., Tawada, M., Yanagisawa, M., Kimura, S., Togawa, N. & Sugibayashi, T., 2013 1 1, 2013 IEEE 10th International Conference on ASIC, ASICON 2013. IEEE Computer Society, 6811826. (Proceedings of International Conference on ASIC).

研究成果: Conference contribution

1 引用 (Scopus)

Error Correction Coding of Stochastic Numbers Using BER Measurement

Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2019 7, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019. Gizopoulos, D., Alexandrescu, D., Papavramidou, P. & Maniatakos, M. (版). Institute of Electrical and Electronics Engineers Inc., p. 243-246 4 p. 8854450. (2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019).

研究成果: Conference contribution

1 引用 (Scopus)

Error correction system using stochastic numbers in symmetric channels and z channels

Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2019 11, 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019. Institute of Electrical and Electronics Engineers Inc., p. 578-581 4 p. 8965039. (2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019).

研究成果: Conference contribution

2 引用 (Scopus)

Exact and fast L1 cache configuration simulation for embedded systems with FIFO/PLRU cache replacement policies

Tawada, M., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011 6 28, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. p. 247-250 4 p. 5783622. (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

研究成果: Conference contribution

4 引用 (Scopus)

Exact and fast L1 cache simulation for embedded systems

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 4 20, Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009. p. 817-822 6 p. 4796581. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

25 引用 (Scopus)

Fast source optimization by clustering algorithm based on lithography properties

Tawada, M., Hashimoto, T., Sakanushi, K., Nojima, S., Kotani, T., Yanagisawa, M. & Togawa, N., 2015, Proceedings of SPIE - The International Society for Optical Engineering. SPIE, 巻 9427. 94270K

研究成果: Conference contribution

FCSCAN: An efficient multiscan-based test compression technique for test cost reduction

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2006 9 19, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. p. 653-658 6 p. 1594760. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 巻数 2006).

研究成果: Conference contribution

15 引用 (Scopus)

FIR filter design on flexible engine/generic ALU array and its dedicated synthesis algorithm

Tamura, R., Honma, M., Togawa, N., Yanagisawa, M., Ohtsuki, T. & Satoh, M., 2008 12 1, Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems. p. 701-704 4 p. 4746120. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

研究成果: Conference contribution

4 引用 (Scopus)

Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems

Asai, D., Yanagisawa, M. & Togawa, N., 2018 1 8, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. IEEE Computer Society, 巻 2017-October. p. 64-67 4 p.

研究成果: Conference contribution

FPGA-based Heterogeneous Solver for Three-Dimensional Routing

Hasegawa, K., Ishikawa, R., Nishizawa, M., Kawamura, K., Tawada, M. & Togawa, N., 2020 1, ASP-DAC 2020 - 25th Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 11-12 2 p. 9045660. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; 巻数 2020-January).

研究成果: Conference contribution

GECOM: Test data compression combined with all unknown response masking

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 8 21, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 577-582 6 p. 4484018. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

5 引用 (Scopus)

Hardware Trojan detection and classification based on steady state learning

Oya, M., Yanagisawa, M. & Togawa, N., 2017 9 19, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., p. 215-220 6 p. 8046225

研究成果: Conference contribution

1 引用 (Scopus)

Hardware Trojan Detection Utilizing Machine Learning Approaches

Hasegawa, K., Shi, Y. & Togawa, N., 2018 9 5, Proceedings - 17th IEEE International Conference on Trust, Security and Privacy in Computing and Communications and 12th IEEE International Conference on Big Data Science and Engineering, Trustcom/BigDataSE 2018. Institute of Electrical and Electronics Engineers Inc., p. 1891-1896 6 p. 8456155

研究成果: Conference contribution

Hardware Trojans classification for gate-level netlists based on machine learning

Hasegawa, K., Oya, M., Yanagisawa, M. & Togawa, N., 2016 10 20, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016. Institute of Electrical and Electronics Engineers Inc., p. 203-206 4 p. 7604700

研究成果: Conference contribution

30 引用 (Scopus)

Hardware Trojans classification for gate-level netlists using multi-layer neural networks

Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 9 19, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., p. 227-232 6 p. 8046227

研究成果: Conference contribution

26 引用 (Scopus)

Hash-Table and balanced-Tree based fib architecture for ccn routers

Shimazaki, K., Aoki, T., Hatano, T., Otsuka, T., Miyazaki, A., Tsuda, T. & Togawa, N., 2016 12 27, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., p. 67-68 2 p. 7799736

研究成果: Conference contribution

1 引用 (Scopus)

High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 9 5, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. p. 164-167 4 p. 4542438. (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT).

研究成果: Conference contribution

9 引用 (Scopus)

High-level synthesis with post-silicon delay tuning for RDR architectures

Hagio, Y., Yanagisawa, M. & Togawa, N., 2013 1 1, ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, p. 194-197 4 p. 6863970. (ISOCC 2013 - 2013 International SoC Design Conference).

研究成果: Conference contribution

2 引用 (Scopus)

Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation

Igarashi, K., Yanagisawa, M. & Togawa, N., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7517027

研究成果: Conference contribution

2 引用 (Scopus)

Implementation evaluation of scan-based attack against a Trivium cipher circuit

Oku, D., Yanagisawa, M. & Togawa, N., 2017 1 3, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., p. 220-223 4 p. 7803938

研究成果: Conference contribution

Implementation of a ROS-based autonomous vehicle on an FPGA board

Hasegawa, K., Takasaki, K., Nishizawa, M., Ishikawa, R., Kawamura, K. & Togawa, N., 2019 12, Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019. Institute of Electrical and Electronics Engineers Inc., p. 457-460 4 p. 8977881. (Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019; 巻数 2019-December).

研究成果: Conference contribution

Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation

Yoshida, S., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516962

研究成果: Conference contribution

Indoor navigation based on real-Time direction information generation using wearable glasses

Iwanaji, R., Nitta, T., Ishikawa, K., Yanagisawa, M. & Togawa, N., 2017 1 3, 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016. Institute of Electrical and Electronics Engineers Inc., 7804754

研究成果: Conference contribution

2 引用 (Scopus)

In-situ timing monitoring methods for variation-resilient designs

Shi, Y. & Togawa, N., 2015 2 5, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February 版 Institute of Electrical and Electronics Engineers Inc., p. 735-738 4 p. 7032886. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 巻数 2015-February, 番号 February).

研究成果: Conference contribution

In-situ Trojan authentication for invalidating hardware-Trojan functions

Oya, M., Shi, Y., Yanagisawa, M. & Togawa, N., 2016 5 25, Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. IEEE Computer Society, 巻 2016-May. p. 152-157 6 p. 7479192

研究成果: Conference contribution

4 引用 (Scopus)

Landmark Seasonal Travel Distribution and Activity Prediction Based on Language-specific Analysis

Bao, S., Yanagisawa, M. & Togawa, N., 2019 1 22, Proceedings - 2018 IEEE International Conference on Big Data, Big Data 2018. Song, Y., Liu, B., Lee, K., Abe, N., Pu, C., Qiao, M., Ahmed, N., Kossmann, D., Saltz, J., Tang, J., He, J., Liu, H. & Hu, X. (版). Institute of Electrical and Electronics Engineers Inc., p. 3628-3637 10 p. 8622103. (Proceedings - 2018 IEEE International Conference on Big Data, Big Data 2018).

研究成果: Conference contribution

Linear and bi-linear interpolation circuits using selector logics and their evaluations

Shio, M., Yanagisawa, M. & Togawa, N., 2014 1 1, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., p. 1436-1439 4 p. 6865415. (Proceedings - IEEE International Symposium on Circuits and Systems).

研究成果: Conference contribution

7 引用 (Scopus)

Low power test compression technique for designs with multiple scan chains

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2005 12 1, Proceedings - 14th Asian Test Symposium, ATS 2005. p. 386-389 4 p. 1575460. (Proceedings of the Asian Test Symposium; 巻数 2005).

研究成果: Conference contribution

17 引用 (Scopus)