• 837 引用
  • 14 h指数
1994 …2020
Pureに変更を加えた場合、すぐここに表示されます。

研究成果 1994 2020

フィルター
Article
2019

A fully-connected ising model embedding method and its evaluation for CMOS annealing machines

Oku, D., Terada, K., Hayashi, M., Yamaoka, M., Tanaka, S. & Togawa, N., 2019 1 1, : : IEICE Transactions on Information and Systems. E102D, 9, p. 1696-1706 11 p.

研究成果: Article

公開
Ising model
Combinatorial optimization
Annealing
Chain length
Ground state
Reference Point
User Preferences
Search Methods
公開
Field programmable gate arrays (FPGA)
Networks (circuits)
1 引用 (Scopus)
Global positioning system
Classifiers
Random Forest
Learning systems
Classify
Bicycles
Smartphones
Sensor
Sensors
Motion
2018
Soft Error
Trigger
Power Consumption
Electric power utilization
Double Sampling
Error-correcting Codes
Data storage equipment
Systematic Error
Crosstalk
Error Correction
2 引用 (Scopus)
Location Estimation
Positioning
Global positioning system
Mobile devices
Mobile Devices
Multilayer Neural Network
Multilayer neural networks
Hardware
Optimization
Evaluation
Approximate Design
Adders
Gears
Formulation
Energy Consumption
Hardware
Logic
Testing
Transition State
Integrated Circuits
3 引用 (Scopus)
Rearrangement
Networks (circuits)
Logic circuits
Mean square error
Inaccurate
2017
High-level Synthesis
Controller
Controllers
Unit
Hardware Design
High-level Synthesis
Bias voltage
Leakage
Data flow graphs
Energy
9 引用 (Scopus)
Learning systems
Machine Learning
Hardware
Support vector machines
Neural networks
1 引用 (Scopus)
Landmarks
Lighting
Count
Safety
Algorithm Design
Extractor
Wire
Evaluation
Networks (circuits)
Partitioning
2 引用 (Scopus)
Random Forest
Feature Extraction
Learning systems
Feature extraction
Hardware
2016
1 引用 (Scopus)
Code Generation
Error-correcting Codes
Clustering
Data storage equipment
One to many
Power Analysis
Power Consumption
Electric power utilization
Noise Reduction
Noise abatement
1 引用 (Scopus)
Extractor
Partitioning
Stream Processing
Consecutive
Count
6 引用 (Scopus)
Quantitative Evaluation
Pattern matching
Pattern Matching
Hardware
Benchmark
2015
2 引用 (Scopus)
High-level Synthesis
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Module
Costs
5 引用 (Scopus)
Scoring
Hardware
Benchmark
Classify
Outsourcing
1 引用 (Scopus)
High-level Synthesis
Latency
List Scheduling
Interconnection
Scheduling
3 引用 (Scopus)
Prediction Error
Insertion
Timing
Networks (circuits)
Checkpoint
1 引用 (Scopus)
High-level Synthesis
Energy Efficient
Clocks
Interconnect
Energy Saving
2 引用 (Scopus)
Hamming distance
Code Generation
Hamming Distance
Minimum Distance
Limiting
2 引用 (Scopus)
Code Generation
Data storage equipment
Error-correcting Codes
Energy
Static random access storage
1 引用 (Scopus)
Side Channel Attacks
Block Cipher
Signature
Cryptography
Chip
2014
5 引用 (Scopus)
Scheduling
High level synthesis
Silicon
Clocks
Energy utilization
High level synthesis

Foreword: Special section on VLSI design and CAD algorithms

Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T. および17人, Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S. I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M. & Watanabe, T., 2014 12 1, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, p. 2366 1 p.

研究成果: Article

5 引用 (Scopus)
Stream Cipher
Shift registers
Signature
Attack
Internal
3 引用 (Scopus)
Side Channel Attacks
Block Cipher
Encryption
Cryptography
Signature
1 引用 (Scopus)
High-level Synthesis
Chip
Interconnect
Energy Consumption
Energy utilization
2 引用 (Scopus)
High-level Synthesis
Voltage
Electric potential
Floorplanning
Energy Saving
2 引用 (Scopus)
Cryptography
2012
Adders
Optical resolving power
Image resolution
Costs
Time delay
1 引用 (Scopus)
Locality
Configuration
Communication
Hierarchical Networks
Multimedia Applications
13 引用 (Scopus)
Energy conservation
Electric potential
Semiconductor devices
Energy efficiency
Scheduling
14 引用 (Scopus)
Networks (circuits)
synthesis
clocks
iteration
High level synthesis
Countermeasures
Side Channel Attacks
Attack
Hardware Implementation
Hardware
2011
1 引用 (Scopus)
Fast Fourier transforms
12 引用 (Scopus)
Scheduling
Error detection
High level synthesis
Embedded systems
Simulators
Hardware
Costs
Capacitance
Greedy Algorithm
Decoupling
Chip
Voltage