戸川 望

研究成果

年別の研究成果 1994 2012 2015 2016 2017 2018 2019 2020 2021 2022

• 150 Conference contribution
• 114 Article
• 14 Paper
• 6 Conference article
• 9 その他
  • 5 Editorial
  • 2 Chapter
  • 1 Letter
  • 1 Review article

年別の研究成果

年別の研究成果

検索結果

• A fully-connected ising model embedding method and its evaluation for CMOS annealing machines

  Oku, D., Terada, K., Hayashi, M., Yamaoka, M., Tanaka, S. & Togawa, N., 2019, In: IEICE Transactions on Information and Systems. E102D, 9, p. 1696-1706 11 p.

  研究成果: Article › 査読

  Open Access

  • Ising model 100%
  • Annealing 62%
  • Combinatorial optimization 46%
  • Ground state 15%
  • Chain length 14%
  7 被引用数 (Scopus)

• A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

  Fujiwara, K., Kawamura, K., Abe, S. Y., Yanagisawa, M. & Togawa, N., 2015 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1392-1405 14 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • Field Programmable Gate Array 79%
  • High level synthesis 64%
  • Field programmable gate arrays (FPGA) 41%
  • Design 31%
  2 被引用数 (Scopus)

• A floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation

  Igawa, K., Yanagisawa, M. & Togawa, N., 2017 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 7, p. 1439-1451 13 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • Leakage 66%
  • High level synthesis 64%
  • Bias voltage 63%
  • Compensation and Redress 38%

• A fault-secure high-level synthesis algorithm for RDR architectures

  Tanaka, S., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 150-165 16 p.

  研究成果: Article › 査読

  • High level synthesis 100%
  • Scheduling 26%
  • Error detection 21%
  12 被引用数 (Scopus)

• A fastweighted adder by reducing partial product for reconstruction in super-resolution

  Yoshihara, H., Yanagisawa, M. & Togawa, N., 2012, In: IPSJ Transactions on System LSI Design Methodology. 5, p. 96-105 10 p.

  研究成果: Article › 査読

  • Adders 100%
  • Optical resolving power 24%
  • Image resolution 19%
  • Time delay 15%
  • Costs 13%

• A fast selector-based subtract-multiplication unit and its application to butterfly unit

  Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 60-69 10 p.

  研究成果: Article › 査読

  • Fast Fourier transforms 100%
  1 被引用数 (Scopus)

• A fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis

  Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1998, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 6, p. 1231-1241 11 p.

  研究成果: Article › 査読

  • Scheduling Algorithm 100%
  • Fast Algorithm 68%
  • Scheduling algorithms 67%
  • Synthesis 61%
  • Connectivity 46%

• A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

  Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, In: IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.

  研究成果: Article › 査読

  • Cryptography 100%
  • Time 43%
  • Computer hardware 11%

• A depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured LUTs

  Togawa, N., Ara, K., Yanagisawa, M. & Ohtsuki, T., 1999 1月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 3, p. 473-481 9 p.

  研究成果: Article › 査読

  • Logic 100%
  • Boolean Networks 60%
  • Minimise 33%
  • Look-up Table 30%
  • Table lookup 25%
  1 被引用数 (Scopus)

• A delay-variation-aware high-level synthesis algorithm for RDR architectures

  Hagio, Y., Yanagisawa, M. & Togawa, N., 2014, In: IPSJ Transactions on System LSI Design Methodology. 7, p. 81-90 10 p.

  研究成果: Article › 査読

  • High level synthesis 100%
  • Scheduling 53%
  • Silicon 10%
  5 被引用数 (Scopus)

• A circuit partitioning algorithm with path delay constraints for multi-FPGA systems

  Togawa, N., 1997 1月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E80-A, 3, p. 494-505 12 p.

  研究成果: Article › 査読

  • Field Programmable Gate Array 100%
  • Critical Path 75%
  • Partitioning 63%
  • Field programmable gate arrays (FPGA) 51%
  • Chip 50%
  3 被引用数 (Scopus)

• A capacitance measurement device for running hardware devices and its evaluations

  Nishizawa, M., Hasegawa, K. & Togawa, N., 2020 9月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E103A, 9, p. 1018-1027 10 p.

  研究成果: Article › 査読

  • Capacitance measurement 100%
  • Capacitance 92%
  • Hardware 84%
  • Evaluation 50%
  • Computer hardware 40%

• A bit-write-reducing and error-correcting code generation method by clustering ECC codewords for non-volatile memories

  Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2016 12月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2398-2411 14 p.

  研究成果: Article › 査読

  • Code Generation 100%
  • Error-correcting Codes 67%
  • Clustering 54%
  • Data storage equipment 34%
  • Crosstalk 15%
  1 被引用数 (Scopus)

• A bitwidth-aware high-level synthesis algorithm using operation chainings for tiled-DR architectures

  Terada, K., Yanagisawa, M. & Togawa, N., 2017 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 12, p. 2911-2924 14 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Architecture 56%
  • Controller 48%
  • Controllers 27%