戸川 望

研究成果

年別の研究成果 1994 2012 2015 2016 2017 2018 2019 2020 2021 2022 2023

• 159 Conference contribution
• 122 Article
• 14 Paper
• 6 Conference article
• 9 その他
  • 5 Editorial
  • 2 Chapter
  • 1 Letter
  • 1 Review article

年別の研究成果

年別の研究成果

検索結果

• Article

  A simultaneous technology mapping, placement, and global routing algorithm for fpgas with path delay constraints

  Togawa, N., Sato, M. & Ohtsuki, T., 1996 1月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E79-A, 3, p. 321-329 9 p.

  研究成果 › 査読

  • Field Programmable Gate Array 100%
  • Routing Algorithm 90%
  • Placement 73%
  • Routing algorithms 64%
  • Routing 49%

• A stayed location estimation method for sparse GPS positioning information based on positioning accuracy and short-time cluster removal

  Iwata, S., Nitta, T., Takayama, T., Yanagisawa, M. & Togawa, N., 2018 5月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 5, p. 831-843 13 p.

  研究成果 › 査読

  • Location Estimation 100%
  • Positioning 83%
  • Global positioning system 52%
  • Mobile Devices 18%
  • Battery 14%
  2 被引用数 (Scopus)

• A thermal-aware high-level synthesis algorithm for RDR architectures through binding and allocation

  Kawamura, K., Yanagisawa, M. & Togawa, N., 2013 1月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 1, p. 312-321 10 p.

  研究成果 › 査読

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Architecture 56%
  • Chip 48%
  • Energy Consumption 38%
  1 被引用数 (Scopus)

• A three-stage annealing method solving slot-placement problems using an ising machine

  Fukada, K., Parizy, M., Tomita, Y. & Togawa, N., 2021, In: IEEE Access. 9, p. 134413-134426 14 p.

  研究成果 › 査読

  Open Access

  • Annealing 100%
  • Combinatorial optimization 88%
  • Electric wiring 43%
  • Length 24%
  • Spin State 22%
  2 被引用数 (Scopus)

• A two-level cache design space exploration system for embedded applications

  Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3238-3247 10 p.

  研究成果 › 査読

  • Design Space Exploration 100%
  • Cache 67%
  • Data storage equipment 18%
  • Embedded systems 14%
  • Energy utilization 10%

• A unified test compression technique for scan stimulus and unknown masking data with no test loss

  Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 12, p. 3514-3523 10 p.

  研究成果 › 査読

  • Masking 100%
  • Compression 73%
  • Cost reduction 73%
  • Masks 68%
  • Unknown 47%

• Bicycle behavior recognition using 3-axis acceleration sensor and 3-axis gyro sensor equipped with smartphone

  Usami, Y., Ishikawa, K., Takayama, T., Yanagisawa, M. & Togawa, N., 2019, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E102A, 8, p. 953-965 13 p.

  研究成果 › 査読

  • Sensor 100%
  • Bicycles 99%
  • Smartphones 80%
  • Sensors 43%
  • Motion 17%
  2 被引用数 (Scopus)

• Bi-partitioning based multiplexer network for field-data extractors

  Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2016 7月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 7, p. 1410-1414 5 p.

  研究成果 › 査読

  • Extractor 100%
  • Partitioning 71%
  • Stream Processing 32%
  • Experimental Results 18%
  • Count 15%
  1 被引用数 (Scopus)

• CAM processor synthesis based on behavioral descriptions

  Togawa, N., Wakui, T., Yoden, T., Terajima, M., Yanagisawa, M. & Ohtsuki, T., 2000 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2464-2473 10 p.

  研究成果 › 査読

  • Associative storage 100%
  • Synthesis 65%
  • Application programs 36%
  • Unit 31%
  • Requirements 14%
  1 被引用数 (Scopus)

• Carrying-mode Free Indoor Positioning Using Smartphone and Smartwatch and Its Evaluations

  Wakaizumi, T. & Togawa, N., 2022, In: Journal of information processing. 30, p. 52-65 14 p.

  研究成果: Article › 査読

  Open Access

  • Smartphones 100%
  • Sensors 31%
  • Navigation systems 30%
  • Angular velocity 16%
  • Global positioning system 13%

• Circuit partitioning algorithm with replication capability for multi-FPGA systems

  Togawa, N., Sato, M. & Ohtsuki, T., 1995 12月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E78-A, 12, p. 1765-1776 12 p.

  研究成果 › 査読

  • Field Programmable Gate Array 100%
  • Chip 81%
  • Replication 71%
  • Partitioning 63%
  • Field programmable gate arrays (FPGA) 51%
  2 被引用数 (Scopus)

• Code generation limiting maximum and minimum hamming distances for non-volatile memories

  Kojo, T., Tawada, M., Yanagisawa, M. & Togawa, N., 2015 12月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2484-2493 10 p.

  研究成果 › 査読

  • Code Generation 100%
  • Hamming distance 72%
  • Limiting 46%
  • Data storage equipment 34%
  • Error-correcting Codes 22%
  2 被引用数 (Scopus)

• ECC-Based bit-write reduction code generation for non-volatile memory

  Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2015 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2494-2504 11 p.

  研究成果: Article › 査読

  • Code Generation 100%
  • Data storage equipment 34%
  • Energy 21%
  • Error-correcting Codes 19%
  • Cell 12%
  2 被引用数 (Scopus)

• Efficient multiplexer networks for field-data extractors and their evaluations

  Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2017 4月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 4, p. 1015-1028 14 p.

  研究成果 › 査読

  • Extractor 100%
  • Wire 54%
  • Evaluation 52%
  • Networks (circuits) 19%
  • Output 19%

• Empirical evaluation and optimization of hardware-Trojan classification for gate-level netlists based on multi-layer neural networks

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2018 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 12, p. 2320-2326 7 p.

  研究成果 › 査読

  • Multilayer Neural Network 100%
  • Hardware security 78%
  • Hardware 74%
  • Multilayer neural networks 62%
  • Optimization 46%
  8 被引用数 (Scopus)

• Energy-efficient high-level synthesis for HDR architectures

  Abe, S. Y., Yanagisawa, M. & Togawa, N., 2012, In: IPSJ Transactions on System LSI Design Methodology. 5, p. 106-117 12 p.

  研究成果 › 査読

  • High level synthesis 100%
  • Energy conservation 31%
  • Electric potential 30%
  • Semiconductor devices 22%
  • Energy efficiency 15%
  13 被引用数 (Scopus)

• Energy-efficient high-level synthesis for HDR architecture with multi-stage clock gating

  Akasaka, H., Abe, S. Y., Yanagisawa, M. & Togawa, N., 2014, In: IPSJ Transactions on System LSI Design Methodology. 7, p. 74-80 7 p.

  研究成果 › 査読

  • High level synthesis 100%
  • Clocks 66%
  • Energy utilization 41%

• Exact, fast and flexible L1 cache configuration simulation for embedded systems

  Tawada, M., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 166-181 16 p.

  研究成果 › 査読

  • Embedded systems 100%
  • Simulators 26%
  • Computer hardware 21%
  • Costs 13%

• Experimental evaluations of parallel tempering on an ising machine

  Mukasa, Y., Tanaka, S. & Togawa, N., 2021, In: IPSJ Transactions on System LSI Design Methodology. 14, p. 27-29 3 p.

  研究成果 › 査読

  Open Access

  • Tempering 100%
  • Combinatorial optimization 97%

• Extension and performance/accuracy formulation for optimal GeAr-based approximate adder designs

  Hayamizu, K., Togawa, N., Yanagisawa, M. & Shi, Y., 2018 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1014-1024 11 p.

  研究成果 › 査読

  • Approximate Design 100%
  • Adders 72%
  • Gears 57%
  • Formulation 41%
  • Energy Consumption 40%
  1 被引用数 (Scopus)

• Fast scheduling and allocation algorithms for entropy CODEC

  Suzuki, K., Togawa, N., Sato, M. & Ohtsuki, T., 1997 1月 1, In: IEICE Transactions on Information and Systems. E80-D, 10, p. 982-992 11 p.

  研究成果 › 査読

  • Scheduling algorithms 100%
  • Flow graphs 89%
  • Entropy 85%
  • High level synthesis 43%
  • Merging 33%

• Floorplan-aware high-level synthesis for generalized distributed-register architectures

  Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3169-3179 11 p.

  研究成果 › 査読

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Architecture 56%
  • Controller 38%
  • Floorplanning 35%
  8 被引用数 (Scopus)

• Floorplan driven architecture and high-level synthesis algorithm for dynamic multiple supply voltages

  Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2013 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 12, p. 2597-2611 15 p.

  研究成果 › 査読

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Voltage 57%
  • Architecture 56%
  • Floorplanning 29%
  2 被引用数 (Scopus)

• Floorplan-driven high-level synthesis for distributed/shared-register architectures

  Ohchi, A., Kohara, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 8月, In: IPSJ Transactions on System LSI Design Methodology. 1, p. 78-90 13 p.

  研究成果 › 査読

  • High level synthesis 100%
  • Scheduling 53%
  • Networks (circuits) 21%
  8 被引用数 (Scopus)

• FPGA-based reconfigurable adaptive FEC

  Shimizu, K., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3036-3046 11 p.

  研究成果 › 査読

  • Field Programmable Gate Array 100%
  • Error Correction 82%
  • Error correction 67%
  • Throughput 55%
  • Field programmable gate arrays (FPGA) 51%
  2 被引用数 (Scopus)

• Generating adversarial examples for hardware-trojan detection at gate-level netlists

  Nozawa, K., Hasegawa, K., Hidano, S., Kiyomoto, S., Hashimoto, K. & Togawa, N., 2021, In: Journal of information processing. 29, p. 236-246 11 p.

  研究成果: Article › 査読

  Open Access

  • Hardware security 100%
  • Networks (circuits) 25%
  • Machine learning 22%
  • Integrated circuit design 19%
  • Integrated circuits 14%
  4 被引用数 (Scopus)

• Greedy algorithm for the on-chip decoupling capacitance optimization to satisfy the voltage drop constraint

  Sode Tanaka, M., Togawa, N., Yanagisawa, M. & Goto, S., 2011 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 12, p. 2482-2489 8 p.

  研究成果 › 査読

  • Capacitance 100%
  • Chip 95%
  • Decoupling 85%
  • Voltage 85%
  • Greedy Algorithm 84%

• Greedy optimization algorithm for the power/ground network design to satisfy the voltage drop constraint

  Sode Tanaka, M., Togawa, N., Yanagisawa, M. & Goto, S., 2011 4月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 4, p. 1082-1090 9 p.

  研究成果 › 査読

  • Network Design 100%
  • Voltage 90%
  • Greedy Algorithm 90%
  • Optimization Algorithm 85%
  • Electric potential 41%
  3 被引用数 (Scopus)

• Guiding Principle for Minor-Embedding in Simulated-Annealing-Based Ising Machines

  Shirai, T., Tanaka, S. & Togawa, N., 2020, In: IEEE Access. 8, p. 210490-210502 13 p., 9268172.

  研究成果: Article › 査読

  Open Access

  • Ising Model 100%
  • Ising model 99%
  • Simulated annealing 63%
  • Combinatorial optimization 51%
  • Statistical mechanics 46%
  2 被引用数 (Scopus)

• Hardware trojan detection and classification based on logic testing utilizing steady state learning

  Oya, M., Yanagisawa, M. & Togawa, N., 2018 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 12, p. 2308-2319 12 p.

  研究成果: Article › 査読

  • Hardware security 100%
  • Hardware 95%
  • Learning 71%
  • Logic 61%
  • Testing 55%
  2 被引用数 (Scopus)

• Hardware-Trojan Detection Based on the Structural Features of Trojan Circuits Using Random Forests

  Kurihara, T. & Togawa, N., 2022 7月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E105A, 7, p. 1049-1060 12 p.

  研究成果 › 査読

  • Random Forest 100%
  • Hardware security 87%
  • Hardware 83%
  • Random forests 72%
  • Networks (circuits) 37%

• Hardware-trojans rank: Quantitative evaluation of security threats at gate-level netlists by pattern matching

  Oya, M., Yamashita, N., Okamura, T., Tsunoo, Y., Yanagisawa, M. & Togawa, N., 2016 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 12, p. 2335-2347 13 p.

  研究成果 › 査読

  • Quantitative Evaluation 100%
  • Hardware security 83%
  • Pattern Matching 82%
  • Hardware 79%
  • Pattern matching 74%
  10 被引用数 (Scopus)

• High-level area/delay/power estimation for low power system VLSIs with gated clocks

  Noda, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 4月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 4, p. 827-834 8 p.

  研究成果 › 査読

  • Power Consumption 100%
  • Power System 80%
  • Clocks 52%
  • High-level Synthesis 30%
  • Electric power utilization 30%
  4 被引用数 (Scopus)

• High-level power optimization based on thread partitioning

  Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3075-3082 8 p.

  研究成果 › 査読

  • Thread 100%
  • Partitioning 77%
  • High level synthesis 66%
  • Optimization 58%
  • Networks (circuits) 42%

• How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins

  Oku, D., Tawada, M., Tanaka, S. & Togawa, N., 2022 1月 1, In: IEEE Transactions on Computers. 71, 1, p. 223-234 12 p.

  研究成果: Article › 査読

  Open Access

  • Ising model 100%
  • Ising Model 73%
  • Annealing 28%
  • Combinatorial optimization 23%
  • Combinatorial Optimization Problem 22%
  2 被引用数 (Scopus)

• Hybrid Annealing Method Based on subQUBO Model Extraction with Multiple Solution Instances

  Atobe, Y., Tawada, M. & Togawa, N., 2022 10月 1, In: IEEE Transactions on Computers. 71, 10, p. 2606-2619 14 p.

  研究成果: Article › 査読

  Open Access

  • Annealing 100%
  • Multiple Solutions 81%
  • Optimization Model 74%
  • Ground State Solution 72%
  • Ising 56%

• Improved launch for higher TDF coverage with fewer test patterns

  Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 8月 1, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29, 8, p. 1294-1299 6 p., 5512687.

  研究成果 › 査読

  • Networks (circuits) 100%

• Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique

  Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2008, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 4, p. 1054-1061 8 p.

  研究成果 › 査読

  • LDPC Codes 100%
  • Architecture 73%
  • Compression 67%
  • Dissipation 65%
  • Energy dissipation 56%

• Maple: A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays

  Togawa, N., Sato, M. & Ohtsuki, T., 1994 12月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E77-A, 12, p. 2028-2038 11 p.

  研究成果 › 査読

  • Field Programmable Gate Array 100%
  • Routing Algorithm 90%
  • Placement 73%
  • Maple 70%
  • Routing algorithms 64%

• Maple-opt: A performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGA's

  Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1998, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17, 9, p. 803-818 16 p.

  研究成果 › 査読

  • Routing algorithms 100%
  • Field programmable gate arrays (FPGA) 80%
  • Networks (circuits) 10%
  7 被引用数 (Scopus)

• Mapping induced subgraph isomorphism problems to ising models and its evaluations by an ising machine

  Yoshimura, N., Tawada, M., Tanaka, S., Arai, J., Yagi, S., Uchiyama, H. & Togawa, N., 2021 4月, In: IEICE Transactions on Information and Systems. E104.D, 4, p. 481-489 9 p.

  研究成果 › 査読

  Open Access

  • Ising model 100%
  • Combinatorial optimization 34%
  • Chemical bonds 23%
  • Graph structures 19%
  • Simulated annealing 15%
  1 被引用数 (Scopus)

• MH ⁴: Multiple-supplyvoltages aware high-level synthesis for highintegrated and highfrequency circuits for HDR architectures

  Abe, S. Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2012, In: ieice electronics express. 9, 17, p. 1414-1422 9 p.

  研究成果 › 査読

  • High level synthesis 100%
  • synthesis 56%
  • Networks (circuits) 43%
  • clocks 13%
  • iteration 12%
  14 被引用数 (Scopus)

• Multi-Objective Trip Planning Based on Ant Colony Optimization Utilizing Trip Records

  Saeki, E., Bao, S., Takayama, T. & Togawa, N., 2022, In: IEEE Access. 10, p. 127825-127844 20 p.

  研究成果 › 査読

  Open Access

  • Pheromone 100%
  • Ant colony optimization 87%
  • Planning 50%
  • Tourism 31%
  • Information technology 23%

• Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms

  Igawa, K., Yanagisawa, M. & Togawa, N., 2016, In: ieice electronics express. 13, 18, 20160641.

  研究成果 › 査読

  • High level synthesis 100%
  • registers 70%
  • platforms 65%
  • Field programmable gate arrays (FPGA) 63%
  • synthesis 56%

• Multi-Spin-Flip Engineering in an Ising Machine

  Shirai, T. & Togawa, N., 2023 3月 1, In: IEEE Transactions on Computers. 72, 3, p. 759-771 13 p.

  研究成果: Article › 査読

  Open Access

  • Ising 100%
  • Hamiltonians 94%
  • Flip 90%
  • Engineering 64%
  • Ising model 62%

• Partially-parallel LDPC decoder achieving high-efficiency message-passing schedule

  Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 4月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 4, p. 969-977 9 p.

  研究成果 › 査読

  • Message Passing 100%
  • High Efficiency 86%
  • Message passing 78%
  • Schedule 77%
  • Iterative decoding 63%
  9 被引用数 (Scopus)

• Performance Comparison of Typical Binary-Integer Encodings in an Ising Machine

  Tamura, K., Shirai, T., Katsura, H., Tanaka, S. & Togawa, N., 2021, In: IEEE Access. 9, p. 81032-81039 8 p., 9435359.

  研究成果: Article › 査読

  Open Access

  • Ising Model 100%
  • Combinatorial optimization 69%
  • Ising model 66%
  • Ground state 31%
  • Ground State 24%
  11 被引用数 (Scopus)

• Power-efficient LDPC decoder architecture based on accelerated message-passing schedule

  Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3602-3612 11 p.

  研究成果 › 査読

  • Message Passing 100%
  • Architecture 81%
  • Message passing 78%
  • Schedule 77%
  • Static random access storage 32%
  5 被引用数 (Scopus)

• Reconfigurable adaptive FEC system based on reed-solomon code with interleaving

  Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2005 7月, In: IEICE Transactions on Information and Systems. E88-D, 7, p. 1526-1537 12 p.

  研究成果 › 査読

  • Reed-Solomon codes 100%
  • Adaptive systems 84%
  • Error correction 80%
  • Computer hardware 35%
  • Network protocols 20%
  3 被引用数 (Scopus)

• R-HTDetector: Robust Hardware-Trojan Detection Based on Adversarial Training

  Hasegawa, K., Hidano, S., Nozawa, K., Kiyomoto, S. & Togawa, N., 2023 2月 1, In: IEEE Transactions on Computers. 72, 2, p. 333-345 13 p.

  研究成果 › 査読

  Open Access

  • Hardware security 100%
  • Hardware 95%
  • Training 82%
  • Machine Learning 36%
  • Machine learning 24%