戸川 望

研究成果

年別の研究成果 1994 2012 2015 2016 2017 2018 2019 2020 2021 2022 2023

• 159 Conference contribution
• 122 Article
• 14 Paper
• 6 Conference article
• 9 その他
  • 5 Editorial
  • 2 Chapter
  • 1 Letter
  • 1 Review article

年別の研究成果

年別の研究成果

検索結果

• Article

  Robust secure scan design against scan-based differential cryptanalysis

  Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2012 1月, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 1, p. 176-181 6 p., 5734887.

  研究成果 › 査読
  22 被引用数 (Scopus)

• Scalable stochastic number duplicators for accuracy-flexible arithmetic circuit design

  Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2020, In: IPSJ Transactions on System LSI Design Methodology. 13, p. 10-20 11 p.

  研究成果: Article › 査読

  Open Access

  • Networks (circuits) 100%
  • Flip flop circuits 52%
  • Logic circuits 51%
  1 被引用数 (Scopus)

• Scan-based attack against DES and Triple DES cryptosystems using scan signatures

  Kodera, H., Yanagisawa, M. & Togawa, N., 2013, In: Journal of information processing. 21, 3, p. 572-579 8 p.

  研究成果 › 査読

  • Cryptography 100%
  • Side channel attack 21%
  2 被引用数 (Scopus)

• Scan-based attack against trivium stream cipher using scan signatures

  Fujishiro, M., Yanagisawa, M. & Togawa, N., 2014 7月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97-A, 7, p. 1444-1451 8 p.

  研究成果 › 査読

  • Stream Ciphers 100%
  • Shift registers 93%
  • Side channel attack 91%
  • Attack 76%
  • Internal 61%
  6 被引用数 (Scopus)

• Scan-based attack on AES through round registers and its countermeasure

  Shi, Y., Togawa, N. & Yanagisawa, M., 2012 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E95-A, 12, p. 2338-2346 9 p.

  研究成果 › 査読

  • Countermeasures 100%
  • Side channel attack 77%
  • Side Channel Attacks 69%
  • Attack 64%
  • Hardware Implementation 64%

• Scan-based side-channel attack against HMAC-SHA-256 circuits based on isolating bit-transition groups using scan signatures

  Oku, D., Yanagisawa, M. & Togawa, N., 2018 2月, In: IPSJ Transactions on System LSI Design Methodology. 11, p. 16-28 13 p.

  研究成果 › 査読

  • Side channel attack 100%
  • Networks (circuits) 44%
  2 被引用数 (Scopus)

• Scan-based side-channel attack against RSA cryptosystems using scan signatures

  Nara, R., Satoh, K., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E93-A, 12, p. 2481-2489 9 p.

  研究成果 › 査読

  • Side Channel Attacks 100%
  • RSA Cryptosystem 91%
  • Side channel attack 74%
  • Cryptography 50%
  • Networks (circuits) 33%
  64 被引用数 (Scopus)

• Scan-based side-channel attack on the camellia block cipher using scan signatures

  Jiang, H., Fujishiro, M., Kodera, H., Yanagisawa, M. & Togawa, N., 2015 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 12, p. 2547-2555 9 p.

  研究成果 › 査読

  • Side Channel Attacks 100%
  • Block Ciphers 77%
  • Side channel attack 74%
  • Chip 38%
  • Chain 34%
  3 被引用数 (Scopus)

• Scan-based side-channel attack on the LED block cipher using scan signatures

  Fujishiro, M., Yanagisawa, M. & Togawa, N., 2014 12月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, p. 2434-2442 9 p.

  研究成果 › 査読

  • Side Channel Attacks 100%
  • Block Ciphers 77%
  • Side channel attack 74%
  • Encryption 71%
  • Cryptography 50%
  4 被引用数 (Scopus)

• Scan vulnerability in elliptic curve cryptosystems

  Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 47-59 13 p.

  研究成果 › 査読

  • Cryptography 100%
  • Networks (circuits) 38%
  • Public key cryptography 23%
  • Side channel attack 21%
  • Monitoring 9%
  6 被引用数 (Scopus)

• Selective low-care coding: A means for test data compression in circuits with multiple scan chains

  Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2006 4月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 4, p. 996-1003 8 p.

  研究成果 › 査読

  • Data Compression 100%
  • Data compression 84%
  • Coding 77%
  • Chain 58%
  • Networks (circuits) 42%
  2 被引用数 (Scopus)

• Simultaneous placement and global routing for transport-processing FPGA layout

  Togawa, N., Sato, M. & Ohtsuki, T., 1996 1月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E79-A, 12, p. 2140-2149 10 p.

  研究成果 › 査読

  • Field Programmable Gate Array 100%
  • Layout 73%
  • Placement 73%
  • Routing 69%
  • Table lookup 57%
  3 被引用数 (Scopus)

• Solving constrained slot placement problems using an ising machine and its evaluations

  Kanamaru, S., Kawamura, K., Tanaka, S., Tomita, Y. & Togawa, N., 2021 2月 1, In: IEICE Transactions on Information and Systems. E104D, 2, p. 226-236 11 p.

  研究成果 › 査読

  Open Access

  • Ising model 100%
  • Simulated annealing 95%
  • Combinatorial optimization 69%
  • Digital circuits 35%
  • Planning 20%
  1 被引用数 (Scopus)

• Speeding-up exact and fast FIFO-based cache configuration simulation

  Tawada, M., Yanagisawa, M. & Togawa, N., 2011, In: ieice electronics express. 8, 14, p. 1161-1167 7 p.

  研究成果 › 査読

  • Simulation 100%
  • configurations 84%
  • Embedded systems 73%
  • central processing units 63%
  • simulation 60%
  3 被引用数 (Scopus)

• Spin-Variable Reduction Method for Handling Linear Equality Constraints in Lsing Machines

  Shirai, T. & Togawa, N., 2023, (Accepted/In press) In: IEEE Transactions on Computers. p. 1-14 14 p.

  研究成果 › 査読

  Open Access

  • Reduction Method 100%
  • Equality Constraints 98%
  • Combinatorial optimization 97%
  • Combinatorial Optimization Problem 96%
  • Linear Constraints 94%

• Stochastic number duplicators based on bit re-arrangement using randomized bit streams

  Ishikawa, R., Tawada, M., Yanagisawa, M. & Togawa, N., 2018 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 7, p. 1002-1013 12 p.

  研究成果 › 査読

  • Rearrangement 100%
  • Logic circuits 21%
  • Networks (circuits) 20%
  • Mean square error 17%
  • Experimental Evaluation 16%
  5 被引用数 (Scopus)

• Sub-operation parallelism optimization in SIMD processor core synthesis

  Kawazu, H., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E88-A, 4, p. 876-883 8 p.

  研究成果 › 査読

  • Parallelism 100%
  • Synthesis 79%
  • Optimization 66%
  • Unit 60%
  • Timing 31%

• Towards optimization of photonic-crystal surface-emitting lasers via quantum annealing

  Inoue, T., Seki, Y., Tanaka, S., Togawa, N., Ishizaki, K. & Noda, S., 2022 11月 21, In: Optics Express. 30, 24, p. 43503-43512 10 p.

  研究成果 › 査読

  Open Access

  • Optics and Photonics 100%
  • crystal surfaces 68%
  • surface emitting lasers 67%
  • Lasers 52%
  • photonics 44%

• Trojan-net classification for gate-level hardware design utilizing boundary net structures

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2020 7月 1, In: IEICE Transactions on Information and Systems. E103D, 7, p. 1618-1622 5 p.

  研究成果 › 査読

  Open Access

  • Hardware security 100%
  • Computer hardware 45%
  • Machine learning 28%
  • Security of data 18%
  3 被引用数 (Scopus)

• Trojan-net feature extraction and its application to hardware-Trojan detection for gate-level netlists using random forest

  Hasegawa, K., Yanagisawa, M. & Togawa, N., 2017 12月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 12, p. 2857-2868 12 p.

  研究成果 › 査読

  • Feature Extraction 100%
  • Random Forest 97%
  • Hardware security 85%
  • Hardware 81%
  • Random forests 70%
  8 被引用数 (Scopus)

• Unified dual-radix architecture for scalable montgomery multiplications in GF(P) and GF(2ⁿ)

  Tanimura, K., Nara, R., Kohara, S., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 9月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 9, p. 2304-2317 14 p.

  研究成果 › 査読

  • Montgomery multiplication 100%
  • Architecture 63%
  • Multiplier 51%
  • Cryptography 47%
  • Clocks 32%

• X-handling for current X-tolerant compactors with more unknowns and maximal compaction

  Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3119-3127 9 p.

  研究成果 › 査読

  • Masking 63%
  • Compaction 57%
  • Unknown 44%
  • Target 39%
  • Error detection 37%