• 856 引用
  • 14 h指数
1994 …2020
Pureに変更を加えた場合、すぐここに表示されます。

研究成果 1994 2020

フィルター
Article
2011
3 引用 (Scopus)
Network Design
Greedy Algorithm
Optimization Algorithm
Voltage
Electric wiring
6 引用 (Scopus)
Cryptography
Networks (circuits)
Public key cryptography
Monitoring
Testing
3 引用 (Scopus)
configurations
Embedded systems
simulation
Simulators
central processing units
2010
Networks (circuits)
47 引用 (Scopus)
RSA Cryptosystem
Side Channel Attacks
Cryptography
Signature
Networks (circuits)
2009
Design Space Exploration
Cache
Data storage equipment
Embedded systems
Configuration
30 引用 (Scopus)
Discriminators
Cryptosystem
Cryptography
Attack
Networks (circuits)
Design Space Exploration
Cache
Data storage equipment
Embedded systems
Energy utilization
8 引用 (Scopus)
High-level Synthesis
Controllers
Floorplanning
Networks (circuits)
Controller
Montgomery multiplication
Cryptography
Multiplier
Clocks
Time delay
2008
3 引用 (Scopus)
Cryptography
Failure analysis
Testing
8 引用 (Scopus)
Scheduling
Networks (circuits)
High level synthesis
LDPC Codes
Dissipation
Energy dissipation
Compression
Clocks
2006
Cryptography
Hardware
9 引用 (Scopus)
Message passing
Message Passing
High Efficiency
Iterative decoding
Schedule
5 引用 (Scopus)
Message passing
Message Passing
Schedule
Static random access storage
Energy dissipation
2 引用 (Scopus)
Data compression
Data Compression
Coding
Networks (circuits)
Encoding

Special section on VLSI Design and CAD Algorithms

Onodera, H., Ikeda, M., Ishihara, T., Isshiki, T., Inoue, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kuga, M., Kurokawa, A., Sato, T., Shibuya, T., Shiraishi, Y., Takagi, K., Takahashi, A., Takeuchi, Y., Togawa, N., Tomiyama, H. および10人, Nakamura, Y., Hamaguchi, K., Miura, Y., Minato, S. I., Yamaguchi, R., Yamada, M., Yuminaka, Y., Watanabe, T., Hashimoto, M. & Miyazaki, M., 2006 12, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3377 1 p.

研究成果: Article

VLSI Design
Computer aided design
2005
1 引用 (Scopus)
Decomposition
3 引用 (Scopus)
Reed-Solomon codes
Adaptive systems
Error correction
Hardware
Communication channels (information theory)
Parallelism
Synthesis
Unit
Optimization
Timing
2004
Hardware
Software
Unit
Application programs
Cycle
2 引用 (Scopus)

FPGA-based reconfigurable adaptive FEC

Shimizu, K., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 12, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3036-3046 11 p.

研究成果: Article

Error correction
Error Correction
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Reconfigurable Systems
Thread
Partitioning
Optimization
Networks (circuits)
High-level Synthesis
2003
Associative storage
Software System
Hardware
Application programs
Memory Function
2 引用 (Scopus)
Hardware/software Partitioning
Hardware
Unit
Timing
Configuration
Simulator
Simulators
Generator
Hardware
Application programs
2002
Energy Levels
Electron energy levels
Energy
High-level Synthesis
Delay Time
3 引用 (Scopus)
Block Matching
Motion Estimation
Motion estimation
Hardware Architecture
Computer hardware description languages
4 引用 (Scopus)
Power System
Power Consumption
Clocks
Electric power utilization
High-level Synthesis
2001
1 引用 (Scopus)
High-level Synthesis
Hardware
Application programs
Graph in graph theory
Hardware Architecture
Hardware/software Partitioning
Hardware
Unit
Digital Signal Processor
Digital signal processors
4 引用 (Scopus)
Delay Estimation
Digital Signal Processor
Digital signal processors
Hardware
Software
2000
9 引用 (Scopus)
Digital Signal Processor
Digital signal processors
Digital signal processing
Application programs
Software System
1 引用 (Scopus)

CAM processor synthesis based on behavioral descriptions

Togawa, N., Wakui, T., Yoden, T., Terajima, M., Yanagisawa, M. & Ohtsuki, T., 2000 12, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2464-2473 10 p.

研究成果: Article

Associative storage
Synthesis
Application programs
Unit
Memory Function
1999
1 引用 (Scopus)
Logic
Boolean Networks
Minimise
Table lookup
Look-up Table
16 引用 (Scopus)
Digital Signal Processor
Digital signal processors
Application programs
kernel
Computer hardware
Routing algorithms
Field programmable gate arrays (FPGA)
Electric power utilization
Networks (circuits)
1998
Scheduling algorithms
Scheduling Algorithm
Fast Algorithm
Synthesis
Connectivity
Data flow graphs
High-level Synthesis
Flow Graphs
Digital signal processing
Data Flow
Table lookup
Look-up Table
Reconfiguration
Field Programmable Gate Array
System Design
7 引用 (Scopus)
Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)
1997
3 引用 (Scopus)
Field Programmable Gate Array
Critical Path
Field programmable gate arrays (FPGA)
Partitioning
Path
Field programmable gate arrays (FPGA)
Networks (circuits)

Fast scheduling and allocation algorithms for entropy CODEC

Suzuki, K., Togawa, N., Sato, M. & Ohtsuki, T., 1997, : : IEICE Transactions on Information and Systems. E80-D, 10, p. 982-992 11 p.

研究成果: Article

Flow graphs
Entropy
Scheduling
Scheduling algorithms
Merging
1996
Routing algorithms
Routing Algorithm
Field Programmable Gate Array
Placement
Path
3 引用 (Scopus)
Field Programmable Gate Array
Placement
Table lookup
Field programmable gate arrays (FPGA)
Layout
1995
2 引用 (Scopus)
Field Programmable Gate Array
Replication
Field programmable gate arrays (FPGA)
Partitioning
Chip