戸川 望

研究成果

年別の研究成果 1994 2012 2015 2016 2017 2018 2019 2020 2021 2022

• 1341 被引用数
• 17 h-index
• 150 Conference contribution
• 114 Article
• 14 Paper
• 6 Conference article
• 9 その他
  • 5 Editorial
  • 2 Chapter
  • 1 Letter
  • 1 Review article

年別の研究成果

年別の研究成果

検索結果

• 2014

  Scan-based side-channel attack on the LED block cipher using scan signatures

  Fujishiro, M., Yanagisawa, M. & Togawa, N., 2014 12月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, p. 2434-2442 9 p.

  研究成果: Article › 査読

  • Side Channel Attacks 100%
  • Block Ciphers 77%
  • Side channel attack 74%
  • Encryption 71%
  • Cryptography 50%
  4 被引用数 (Scopus)
• 2013

  A high-speed trace-driven cache configuration simulator for dual-core processor L1 caches

  Tawada, M., Yanagisawa, M. & Togawa, N., 2013 6月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 6, p. 1283-1292 10 p.

  研究成果: Article › 査読

  • Cache 100%
  • Simulator 86%
  • High Speed 82%
  • Data structures 55%
  • Trace 54%

• A thermal-aware high-level synthesis algorithm for RDR architectures through binding and allocation

  Kawamura, K., Yanagisawa, M. & Togawa, N., 2013 1月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 1, p. 312-321 10 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Architecture 56%
  • Chip 48%
  • Energy Consumption 38%
  1 被引用数 (Scopus)

• Floorplan driven architecture and high-level synthesis algorithm for dynamic multiple supply voltages

  Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2013 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 12, p. 2597-2611 15 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Voltage 57%
  • Architecture 56%
  • Floorplanning 29%
  2 被引用数 (Scopus)

• Scan-based attack against DES and Triple DES cryptosystems using scan signatures

  Kodera, H., Yanagisawa, M. & Togawa, N., 2013, In: Journal of information processing. 21, 3, p. 572-579 8 p.

  研究成果: Article › 査読

  • Cryptography 100%
  • Side channel attack 21%
  2 被引用数 (Scopus)
• 2012

  A fastweighted adder by reducing partial product for reconstruction in super-resolution

  Yoshihara, H., Yanagisawa, M. & Togawa, N., 2012, In: IPSJ Transactions on System LSI Design Methodology. 5, p. 96-105 10 p.

  研究成果: Article › 査読

  • Adders 100%
  • Optical resolving power 24%
  • Image resolution 19%
  • Time delay 15%
  • Costs 13%

• A locality-aware hybrid NoC configuration algorithm utilizing the communication volume among IP cores

  Lee, S., Yanagisawa, M. & Togawa, N., 2012 9月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E95-A, 9, p. 1538-1549 12 p.

  研究成果: Article › 査読

  • Network on chip 100%
  • Intellectual property core 63%
  • Locality 59%
  • Network-on-chip 56%
  • Communication 45%
  1 被引用数 (Scopus)

• Energy-efficient high-level synthesis for HDR architectures

  Abe, S. Y., Yanagisawa, M. & Togawa, N., 2012, In: IPSJ Transactions on System LSI Design Methodology. 5, p. 106-117 12 p.

  研究成果: Article › 査読

  • High level synthesis 100%
  • Energy conservation 31%
  • Electric potential 30%
  • Semiconductor devices 22%
  • Energy efficiency 15%
  13 被引用数 (Scopus)

• MH ⁴: Multiple-supplyvoltages aware high-level synthesis for highintegrated and highfrequency circuits for HDR architectures

  Abe, S. Y., Shi, Y., Yanagisawa, M. & Togawa, N., 2012, In: ieice electronics express. 9, 17, p. 1414-1422 9 p.

  研究成果: Article › 査読

  • High level synthesis 100%
  • synthesis 56%
  • Networks (circuits) 43%
  • clocks 13%
  • iteration 12%
  14 被引用数 (Scopus)

• Robust secure scan design against scan-based differential cryptanalysis

  Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2012 1月, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 1, p. 176-181 6 p., 5734887.

  研究成果: Article › 査読
  22 被引用数 (Scopus)

• Scan-based attack on AES through round registers and its countermeasure

  Shi, Y., Togawa, N. & Yanagisawa, M., 2012 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E95-A, 12, p. 2338-2346 9 p.

  研究成果: Article › 査読

  • Countermeasures 100%
  • Side channel attack 77%
  • Side Channel Attacks 69%
  • Attack 64%
  • Hardware Implementation 64%
• 2011

  A fast selector-based subtract-multiplication unit and its application to butterfly unit

  Tsukamoto, Y., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 60-69 10 p.

  研究成果: Article › 査読

  • Fast Fourier transforms 100%
  1 被引用数 (Scopus)

• A fault-secure high-level synthesis algorithm for RDR architectures

  Tanaka, S., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 150-165 16 p.

  研究成果: Article › 査読

  • High level synthesis 100%
  • Scheduling 26%
  • Error detection 21%
  12 被引用数 (Scopus)

• Exact, fast and flexible L1 cache configuration simulation for embedded systems

  Tawada, M., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 166-181 16 p.

  研究成果: Article › 査読

  • Embedded systems 100%
  • Simulators 26%
  • Computer hardware 21%
  • Costs 13%

• Greedy algorithm for the on-chip decoupling capacitance optimization to satisfy the voltage drop constraint

  Sode Tanaka, M., Togawa, N., Yanagisawa, M. & Goto, S., 2011 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 12, p. 2482-2489 8 p.

  研究成果: Article › 査読

  • Capacitance 100%
  • Chip 95%
  • Decoupling 85%
  • Voltage 85%
  • Greedy Algorithm 84%

• Greedy optimization algorithm for the power/ground network design to satisfy the voltage drop constraint

  Sode Tanaka, M., Togawa, N., Yanagisawa, M. & Goto, S., 2011 4月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 4, p. 1082-1090 9 p.

  研究成果: Article › 査読

  • Network Design 100%
  • Voltage 90%
  • Greedy Algorithm 90%
  • Optimization Algorithm 85%
  • Electric potential 41%
  3 被引用数 (Scopus)

• Scan vulnerability in elliptic curve cryptosystems

  Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 47-59 13 p.

  研究成果: Article › 査読

  • Cryptography 100%
  • Networks (circuits) 38%
  • Public key cryptography 23%
  • Side channel attack 21%
  • Monitoring 9%
  6 被引用数 (Scopus)

• Speeding-up exact and fast FIFO-based cache configuration simulation

  Tawada, M., Yanagisawa, M. & Togawa, N., 2011, In: ieice electronics express. 8, 14, p. 1161-1167 7 p.

  研究成果: Article › 査読

  • Simulation 100%
  • configurations 84%
  • Embedded systems 73%
  • central processing units 63%
  • simulation 60%
  3 被引用数 (Scopus)
• 2010

  Improved launch for higher TDF coverage with fewer test patterns

  Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 8月 1, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29, 8, p. 1294-1299 6 p., 5512687.

  研究成果: Article › 査読

  • Networks (circuits) 100%

• Scan-based side-channel attack against RSA cryptosystems using scan signatures

  Nara, R., Satoh, K., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E93-A, 12, p. 2481-2489 9 p.

  研究成果: Article › 査読

  • Side Channel Attacks 100%
  • RSA Cryptosystem 91%
  • Side channel attack 74%
  • Cryptography 50%
  • Networks (circuits) 33%
  60 被引用数 (Scopus)
• 2009

  An l1 cache design space exploration system for embedded applications

  Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 1月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 6, p. 1442-1453 12 p.

  研究成果: Article › 査読

  • Design Space Exploration 100%
  • Cache 67%
  • Data storage equipment 27%
  • Embedded systems 21%
  • Configuration 10%

• A scan-based attack based on discriminators for AES cryptosystems

  Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3229-3237 9 p.

  研究成果: Article › 査読

  • Discriminators 100%
  • Cryptosystem 94%
  • Attack 81%
  • Cryptography 72%
  • Chain 50%
  43 被引用数 (Scopus)

• A two-level cache design space exploration system for embedded applications

  Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3238-3247 10 p.

  研究成果: Article › 査読

  • Design Space Exploration 100%
  • Cache 67%
  • Data storage equipment 18%
  • Embedded systems 14%
  • Energy utilization 10%

• Floorplan-aware high-level synthesis for generalized distributed-register architectures

  Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3169-3179 11 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Architecture 56%
  • Controller 38%
  • Floorplanning 35%
  8 被引用数 (Scopus)

• Unified dual-radix architecture for scalable montgomery multiplications in GF(P) and GF(2ⁿ)

  Tanimura, K., Nara, R., Kohara, S., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 9月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 9, p. 2304-2317 14 p.

  研究成果: Article › 査読

  • Montgomery multiplication 100%
  • Architecture 63%
  • Multiplier 51%
  • Cryptography 47%
  • Clocks 32%

• X-handling for current X-tolerant compactors with more unknowns and maximal compaction

  Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3119-3127 9 p.

  研究成果: Article › 査読

  • Masking 63%
  • Compaction 57%
  • Unknown 44%
  • Target 39%
  • Error detection 37%
• 2008

  A secure test technique for pipelined advanced encryption standard

  Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 3月, In: IEICE Transactions on Information and Systems. E91-D, 3, p. 776-780 5 p.

  研究成果: Article › 査読

  • Cryptography 100%
  • Failure analysis 52%
  • Testing 31%
  3 被引用数 (Scopus)

• A unified test compression technique for scan stimulus and unknown masking data with no test loss

  Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 1月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 12, p. 3514-3523 10 p.

  研究成果: Article › 査読

  • Masking 100%
  • Compression 73%
  • Cost reduction 73%
  • Masks 68%
  • Unknown 47%

• Floorplan-driven high-level synthesis for distributed/shared-register architectures

  Ohchi, A., Kohara, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 8月, In: IPSJ Transactions on System LSI Design Methodology. 1, p. 78-90 13 p.

  研究成果: Article › 査読

  • High level synthesis 100%
  • Scheduling 53%
  • Networks (circuits) 21%
  8 被引用数 (Scopus)

• Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique

  Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2008 1月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 4, p. 1054-1061 8 p.

  研究成果: Article › 査読

  • LDPC Codes 100%
  • Architecture 73%
  • Compression 67%
  • Dissipation 65%
  • Energy dissipation 56%
• 2006

  A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

  Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, In: IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.

  研究成果: Article › 査読

  • Cryptography 100%
  • Time 43%
  • Computer hardware 11%

• Partially-parallel LDPC decoder achieving high-efficiency message-passing schedule

  Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 4月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 4, p. 969-977 9 p.

  研究成果: Article › 査読

  • Message Passing 100%
  • High Efficiency 86%
  • Message passing 78%
  • Schedule 77%
  • Iterative decoding 63%
  9 被引用数 (Scopus)

• Power-efficient LDPC decoder architecture based on accelerated message-passing schedule

  Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3602-3612 11 p.

  研究成果: Article › 査読

  • Message Passing 100%
  • Architecture 81%
  • Message passing 78%
  • Schedule 77%
  • Static random access storage 32%
  5 被引用数 (Scopus)

• Selective low-care coding: A means for test data compression in circuits with multiple scan chains

  Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2006 4月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 4, p. 996-1003 8 p.

  研究成果: Article › 査読

  • Data Compression 100%
  • Data compression 84%
  • Coding 77%
  • Chain 58%
  • Networks (circuits) 42%
  2 被引用数 (Scopus)
• 2005

  A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition

  Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005 7月, In: IEICE Transactions on Information and Systems. E88-D, 7, p. 1340-1349 10 p.

  研究成果: Article › 査読

  • Decomposition 100%
  • Set theory 88%
  1 被引用数 (Scopus)

• Reconfigurable adaptive FEC system based on reed-solomon code with interleaving

  Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2005 7月, In: IEICE Transactions on Information and Systems. E88-D, 7, p. 1526-1537 12 p.

  研究成果: Article › 査読

  • Reed-Solomon codes 100%
  • Adaptive systems 84%
  • Error correction 80%
  • Computer hardware 35%
  • Network protocols 20%
  3 被引用数 (Scopus)

• Sub-operation parallelism optimization in SIMD processor core synthesis

  Kawazu, H., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005 1月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E88-A, 4, p. 876-883 8 p.

  研究成果: Article › 査読

  • Parallelism 100%
  • Synthesis 79%
  • Optimization 66%
  • Unit 60%
  • Timing 31%
• 2004

  A hardware/software cosynthesis algorithm for processors with heterogeneous datapaths

  Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 4月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 4, p. 830-836 7 p.

  研究成果: Article › 査読

  • Hardware 100%
  • Software 73%
  • Banks 50%
  • Computer hardware 48%
  • Unit 42%

• FPGA-based reconfigurable adaptive FEC

  Shimizu, K., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3036-3046 11 p.

  研究成果: Article › 査読

  • Field Programmable Gate Array 100%
  • Error Correction 82%
  • Error correction 67%
  • Throughput 55%
  • Field programmable gate arrays (FPGA) 51%
  2 被引用数 (Scopus)

• High-level power optimization based on thread partitioning

  Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3075-3082 8 p.

  研究成果: Article › 査読

  • Thread 100%
  • Partitioning 77%
  • High level synthesis 66%
  • Optimization 58%
  • Networks (circuits) 42%
• 2003

  A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

  Togawa, N., Totsuka, T., Wakui, T., Yanagisawa, M. & Ohtsuki, T., 2003 5月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 5, p. 1082-1092 11 p.

  研究成果: Article › 査読

  • Software System 100%
  • Associative storage 99%
  • Hardware 87%
  • Computer hardware 42%
  • Application programs 35%

• A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions

  Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2003 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3218-3224 7 p.

  研究成果: Article › 査読

  • Timing 100%
  • Unit 87%
  • Computer hardware 74%
  • Configuration 66%
  • Architecture 46%
  2 被引用数 (Scopus)

• A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

  Togawa, N., Kasahara, K., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3099-3109 11 p.

  研究成果: Article › 査読

  • Simulator 100%
  • Generator 56%
  • Simulators 56%
  • Computer hardware 45%
  • Unit 42%
• 2002

  A high-level energy-optimizing algorithm for system VLSIs based on area/time/power estimation

  Noda, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2655-2666 12 p.

  研究成果: Article › 査読

  • Energy Levels 100%
  • Electron energy levels 96%
  • Energy 44%
  • High-level Synthesis 32%
  • Delay Time 22%

• An algorithm and a flexible architecture for fast block-matching motion estimation

  Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2603-2611 9 p.

  研究成果: Article › 査読

  • Block Matching 100%
  • Motion Estimation 82%
  • Architecture 55%
  • Motion estimation 53%
  • Hardware Architecture 38%
  3 被引用数 (Scopus)

• High-level area/delay/power estimation for low power system VLSIs with gated clocks

  Noda, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 4月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 4, p. 827-834 8 p.

  研究成果: Article › 査読

  • Power Consumption 100%
  • Power System 80%
  • Clocks 52%
  • High-level Synthesis 30%
  • Electric power utilization 30%
  4 被引用数 (Scopus)
• 2001

  An area/time optimizing algorithm in high-level synthesis of control-based hardwares

  Togawa, N., Ienaga, M., Yanagisawa, M. & Ohsuki, T., 2001 5月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 5, p. 1166-1176 11 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Hardware 61%
  • Hardware Architecture 29%
  • Computer hardware 29%
  1 被引用数 (Scopus)

• Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

  Togawa, N., Kataoka, Y., Miyaoka, Y., Yanagisawa, M. & Ohsuki, T., 2001 11月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2639-2647 9 p.

  研究成果: Article › 査読

  • Delay Estimation 100%
  • Digital Signal Processor 100%
  • Hardware 63%
  • Digital signal processors 57%
  • Software 47%
  4 被引用数 (Scopus)
• 2000

  A hardware/software cosynthesis system for digital signal processor cores with two types of register files

  Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2000 1月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 3, p. 442-451 10 p.

  研究成果: Article › 査読

  • Digital Signal Processor 100%
  • Software System 72%
  • Hardware 63%
  • Digital signal processors 57%
  • Digital Signal Processing 37%
  9 被引用数 (Scopus)

• CAM processor synthesis based on behavioral descriptions

  Togawa, N., Wakui, T., Yoden, T., Terajima, M., Yanagisawa, M. & Ohtsuki, T., 2000 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2464-2473 10 p.

  研究成果: Article › 査読

  • Associative storage 100%
  • Synthesis 65%
  • Application programs 36%
  • Unit 31%
  • Requirements 14%
  1 被引用数 (Scopus)