Nozomu Togawa

2011

Greedy algorithm for the on-chip decoupling capacitance optimization to satisfy the voltage drop constraint

Sode Tanaka, M., Togawa, N., Yanagisawa, M. & Goto, S., 2011 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 12, p. 2482-2489 8 p.

研究成果: Article

Greedy optimization algorithm for the power/ground network design to satisfy the voltage drop constraint

Sode Tanaka, M., Togawa, N., Yanagisawa, M. & Goto, S., 2011 4, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 4, p. 1082-1090 9 p.

研究成果: Article

3 引用（Scopus）

Scan vulnerability in elliptic curve cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2011 12 5, ： : IPSJ Transactions on System LSI Design Methodology. 4, p. 47-59 13 p.

研究成果: Article

6 引用（Scopus）

Speeding-up exact and fast FIFO-based cache configuration simulation

Tawada, M., Yanagisawa, M. & Togawa, N., 2011, ： : ieice electronics express. 8, 14, p. 1161-1167 7 p.

研究成果: Article

3 引用（Scopus）

2010

Improved launch for higher TDF coverage with fewer test patterns

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 8 1, ： : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29, 8, p. 1294-1299 6 p., 5512687.

研究成果: Article

Scan-based side-channel attack against RSA cryptosystems using scan signatures

Nara, R., Satoh, K., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E93-A, 12, p. 2481-2489 9 p.

研究成果: Article

48 引用（Scopus）

2009

An l1 cache design space exploration system for embedded applications

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 1 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 6, p. 1442-1453 12 p.

研究成果: Article

A scan-based attack based on discriminators for AES cryptosystems

Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3229-3237 9 p.

研究成果: Article

32 引用（Scopus）

A two-level cache design space exploration system for embedded applications

Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3238-3247 10 p.

研究成果: Article

Floorplan-aware high-level synthesis for generalized distributed-register architectures

Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3169-3179 11 p.

研究成果: Article

8 引用（Scopus）

Unified dual-radix architecture for scalable montgomery multiplications in GF(P) and GF(2ⁿ)

Tanimura, K., Nara, R., Kohara, S., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 9, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 9, p. 2304-2317 14 p.

研究成果: Article

X-handling for current X-tolerant compactors with more unknowns and maximal compaction

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3119-3127 9 p.

研究成果: Article

2008

A secure test technique for pipelined advanced encryption standard

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 3, ： : IEICE Transactions on Information and Systems. E91-D, 3, p. 776-780 5 p.

研究成果: Article

3 引用（Scopus）

A unified test compression technique for scan stimulus and unknown masking data with no test loss

Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 1 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 12, p. 3514-3523 10 p.

研究成果: Article

Floorplan-driven high-level synthesis for distributed/shared-register architectures

Ohchi, A., Kohara, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 8 1, ： : IPSJ Transactions on System LSI Design Methodology. 1, p. 78-90 13 p.

研究成果: Article

8 引用（Scopus）

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2008 1 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 4, p. 1054-1061 8 p.

研究成果: Article

2006

A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006 1 1, ： : IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.

研究成果: Article

Partially-parallel LDPC decoder achieving high-efficiency message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 4, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 4, p. 969-977 9 p.

研究成果: Article

9 引用（Scopus）

Power-efficient LDPC decoder architecture based on accelerated message-passing schedule

Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3602-3612 11 p.

研究成果: Article

5 引用（Scopus）

Selective low-care coding: A means for test data compression in circuits with multiple scan chains

Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2006 4, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 4, p. 996-1003 8 p.

研究成果: Article

2 引用（Scopus）

2005

A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005 7, ： : IEICE Transactions on Information and Systems. E88-D, 7, p. 1340-1349 10 p.

研究成果: Article

1 引用（Scopus）

Reconfigurable adaptive FEC system based on reed-solomon code with interleaving

Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2005 7, ： : IEICE Transactions on Information and Systems. E88-D, 7, p. 1526-1537 12 p.

研究成果: Article

3 引用（Scopus）

Sub-operation parallelism optimization in SIMD processor core synthesis

Kawazu, H., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005 1 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E88-A, 4, p. 876-883 8 p.

研究成果: Article

2004

A hardware/software cosynthesis algorithm for processors with heterogeneous datapaths

Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 4, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 4, p. 830-836 7 p.

研究成果: Article

FPGA-based reconfigurable adaptive FEC

Shimizu, K., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3036-3046 11 p.

研究成果: Article

2 引用（Scopus）

High-level power optimization based on thread partitioning

Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3075-3082 8 p.

研究成果: Article

2003

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

Togawa, N., Totsuka, T., Wakui, T., Yanagisawa, M. & Ohtsuki, T., 2003 5, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 5, p. 1082-1092 11 p.

研究成果: Article

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions

Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2003 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3218-3224 7 p.

研究成果: Article

2 引用（Scopus）

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

Togawa, N., Kasahara, K., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3099-3109 11 p.

研究成果: Article

2002

A high-level energy-optimizing algorithm for system VLSIs based on area/time/power estimation

Noda, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2655-2666 12 p.

研究成果: Article

An algorithm and a flexible architecture for fast block-matching motion estimation

Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2603-2611 9 p.

研究成果: Article

3 引用（Scopus）

High-level area/delay/power estimation for low power system VLSIs with gated clocks

Noda, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 4, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 4, p. 827-834 8 p.

研究成果: Article

4 引用（Scopus）

2001

An area/time optimizing algorithm in high-level synthesis of control-based hardwares

Togawa, N., Ienaga, M., Yanagisawa, M. & Ohsuki, T., 2001 5, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 5, p. 1166-1176 11 p.

研究成果: Article

1 引用（Scopus）

Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

Togawa, N., Kataoka, Y., Miyaoka, Y., Yanagisawa, M. & Ohsuki, T., 2001 11, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2639-2647 9 p.

研究成果: Article

4 引用（Scopus）

2000

A hardware/software cosynthesis system for digital signal processor cores with two types of register files

Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2000 1 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 3, p. 442-451 10 p.

研究成果: Article

9 引用（Scopus）

CAM processor synthesis based on behavioral descriptions

Togawa, N., Wakui, T., Yoden, T., Terajima, M., Yanagisawa, M. & Ohtsuki, T., 2000 12 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2464-2473 10 p.

研究成果: Article

1 引用（Scopus）

1999

A depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured LUTs

Togawa, N., Ara, K., Yanagisawa, M. & Ohtsuki, T., 1999 1 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 3, p. 473-481 9 p.

研究成果: Article

1 引用（Scopus）

A hard ware/S oft ware cosynthesis system for digital signal processor cores

Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1999 1 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 11, p. 2325-2327 3 p.

研究成果: Article

16 引用（Scopus）

A simultaneous placement and global routing algorithm for FPGAs with power optimization

Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1999 1 1, ： : Journal of Circuits, Systems and Computers. 9, 1-2, p. 99-112 14 p.

研究成果: Article

1998

A fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis

Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1998 1 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 6, p. 1231-1241 11 p.

研究成果: Article

A high-level synthesis system for digital signal processing based on data-flow graph enumeration

Togawa, N., Hisakl, T., Yanagisawa, M. & Ohtsuku, T., 1998 1 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2563-2575 13 p.

研究成果: Article

An FPGA layout reconfiguration algorithm based on global routes for engineering changes in system design specifications

Togawa, N., Hagi, K., Yanagisawa, M. & Ohtsuki, T., 1998 1 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 5, p. 873-884 12 p.

研究成果: Article

Maple-opt: A performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGA's

Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1998 12 1, ： : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17, 9, p. 803-818 16 p.

研究成果: Article

7 引用（Scopus）

1997

A circuit partitioning algorithm with path delay constraints for multi-FPGA systems

Togawa, N., 1997 1 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E80-A, 3, p. 494-505 12 p.

研究成果: Article

3 引用（Scopus）

A performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems

Togawa, N., Sato, M. & Ohtsuki, T., 1997 10, ： : Journal of Circuits, Systems and Computers. 7, 5, p. 373-393 21 p.

研究成果: Article

Fast scheduling and allocation algorithms for entropy CODEC

Suzuki, K., Togawa, N., Sato, M. & Ohtsuki, T., 1997 1 1, ： : IEICE Transactions on Information and Systems. E80-D, 10, p. 982-992 11 p.

研究成果: Article

1996

A simultaneous technology mapping, placement, and global routing algorithm for fpgas with path delay constraints

Togawa, N., Sato, M. & Ohtsuki, T., 1996 1 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E79-A, 3, p. 321-329 9 p.

研究成果: Article

Simultaneous placement and global routing for transport-processing FPGA layout

Togawa, N., Sato, M. & Ohtsuki, T., 1996 1 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E79-A, 12, p. 2140-2149 10 p.

研究成果: Article

3 引用（Scopus）

1995

Circuit partitioning algorithm with replication capability for multi-FPGA systems

Togawa, N., Sato, M. & Ohtsuki, T., 1995 12 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E78-A, 12, p. 1765-1776 12 p.

研究成果: Article

2 引用（Scopus）

1994

Maple: A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays

Togawa, N., Sato, M. & Ohtsuki, T., 1994 12 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E77-A, 12, p. 2028-2038 11 p.

研究成果: Article

戸川 望

戸川望