年単位の研究成果
研究成果 1994 2020
- 50 - 100 / 102 件中
- 出版年、タイトル （降順）
2011
3
引用
(Scopus)
Greedy optimization algorithm for the power/ground network design to satisfy the voltage drop constraint
Sode Tanaka, M., Togawa, N., Yanagisawa, M. & Goto, S., 2011 4, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 4, p. 1082-1090 9 p.研究成果: Article
Network Design
Greedy Algorithm
Optimization Algorithm
Voltage
Electric wiring
6
引用
(Scopus)
Scan vulnerability in elliptic curve cryptosystems
Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2011, ： : IPSJ Transactions on System LSI Design Methodology. 4, p. 47-59 13 p.研究成果: Article
Cryptography
Networks (circuits)
Public key cryptography
Monitoring
Testing
3
引用
(Scopus)
Speeding-up exact and fast FIFO-based cache configuration simulation
Tawada, M., Yanagisawa, M. & Togawa, N., 2011, ： : IEICE Electronics Express. 8, 14, p. 1161-1167 7 p.研究成果: Article
configurations
Embedded systems
simulation
Simulators
central processing units
2010
Improved launch for higher TDF coverage with fewer test patterns
Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2010 8, ： : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29, 8, p. 1294-1299 6 p., 5512687.研究成果: Article
Networks (circuits)
47
引用
(Scopus)
Scan-based side-channel attack against RSA cryptosystems using scan signatures
Nara, R., Satoh, K., Yanagisawa, M., Ohtsuki, T. & Togawa, N., 2010 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E93-A, 12, p. 2481-2489 9 p.研究成果: Article
RSA Cryptosystem
Side Channel Attacks
Cryptography
Signature
Networks (circuits)
2009
An l1 cache design space exploration system for embedded applications
Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 6, p. 1442-1453 12 p.研究成果: Article
Design Space Exploration
Cache
Data storage equipment
Embedded systems
Configuration
30
引用
(Scopus)
A scan-based attack based on discriminators for AES cryptosystems
Nara, R., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3229-3237 9 p.研究成果: Article
Discriminators
Cryptosystem
Cryptography
Attack
Networks (circuits)
A two-level cache design space exploration system for embedded applications
Tojo, N., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3238-3247 10 p.研究成果: Article
Design Space Exploration
Cache
Data storage equipment
Embedded systems
Energy utilization
8
引用
(Scopus)
Floorplan-aware high-level synthesis for generalized distributed-register architectures
Ohchi, A., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3169-3179 11 p.研究成果: Article
High-level Synthesis
Controllers
Floorplanning
Networks (circuits)
Controller
Unified dual-radix architecture for scalable montgomery multiplications in GF(P) and GF(2n)
Tanimura, K., Nara, R., Kohara, S., Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 9, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 9, p. 2304-2317 14 p.研究成果: Article
Montgomery multiplication
Cryptography
Multiplier
Clocks
Time delay
X-handling for current X-tolerant compactors with more unknowns and maximal compaction
Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2009 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 12, p. 3119-3127 9 p.研究成果: Article
Compaction
Masking
Unknown
Error detection
Masks
2008
3
引用
(Scopus)
A secure test technique for pipelined advanced encryption standard
Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 3, ： : IEICE Transactions on Information and Systems. E91-D, 3, p. 776-780 5 p.研究成果: Article
Cryptography
Failure analysis
Testing
A unified test compression technique for scan stimulus and unknown masking data with no test loss
Shi, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 12, p. 3514-3523 10 p.研究成果: Article
Masking
Cost reduction
Masks
Compression
Unknown
8
引用
(Scopus)
Floorplan-driven high-level synthesis for distributed/shared-register architectures
Ohchi, A., Kohara, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2008 8, ： : IPSJ Transactions on System LSI Design Methodology. 1, p. 78-90 13 p.研究成果: Article
Scheduling
Networks (circuits)
High level synthesis
Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique
Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2008, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 4, p. 1054-1061 8 p.研究成果: Article
LDPC Codes
Dissipation
Energy dissipation
Compression
Clocks
2006
A fast elliptic curve cryptosystem LSI embedding word-based montgomery multiplier
Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2006, ： : IEICE Transactions on Electronics. E89-C, 3, p. 243-249 7 p.研究成果: Article
Cryptography
Hardware
9
引用
(Scopus)
Partially-parallel LDPC decoder achieving high-efficiency message-passing schedule
Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 4, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 4, p. 969-977 9 p.研究成果: Article
Message passing
Message Passing
High Efficiency
Iterative decoding
Schedule
5
引用
(Scopus)
Power-efficient LDPC decoder architecture based on accelerated message-passing schedule
Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T. & Goto, S., 2006 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3602-3612 11 p.研究成果: Article
Message passing
Message Passing
Schedule
Static random access storage
Energy dissipation
2
引用
(Scopus)
Selective low-care coding: A means for test data compression in circuits with multiple scan chains
Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M. & Ohtsuki, T., 2006 4, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 4, p. 996-1003 8 p.研究成果: Article
Data compression
Data Compression
Coding
Networks (circuits)
Encoding
Special section on VLSI Design and CAD Algorithms
Onodera, H., Ikeda, M., Ishihara, T., Isshiki, T., Inoue, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kuga, M., Kurokawa, A., Sato, T., Shibuya, T., Shiraishi, Y., Takagi, K., Takahashi, A., Takeuchi, Y., Togawa, N., Tomiyama, H. および10人, , 2006 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3377 1 p.研究成果: Article
VLSI Design
Computer aided design
2005
1
引用
(Scopus)
A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition
Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2005 7, ： : IEICE Transactions on Information and Systems. E88-D, 7, p. 1340-1349 10 p.研究成果: Article
Decomposition
3
引用
(Scopus)
Reconfigurable adaptive FEC system based on reed-solomon code with interleaving
Shimizu, K., Togawa, N., Ikenaga, T. & Goto, S., 2005 7, ： : IEICE Transactions on Information and Systems. E88-D, 7, p. 1526-1537 12 p.研究成果: Article
Reed-Solomon codes
Adaptive systems
Error correction
Hardware
Communication channels (information theory)
Sub-operation parallelism optimization in SIMD processor core synthesis
Kawazu, H., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2005, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E88-A, 4, p. 876-883 8 p.研究成果: Article
Parallelism
Synthesis
Unit
Optimization
Timing
2004
A hardware/software cosynthesis algorithm for processors with heterogeneous datapaths
Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 4, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 4, p. 830-836 7 p.研究成果: Article
Hardware
Software
Unit
Application programs
Cycle
2
引用
(Scopus)
FPGA-based reconfigurable adaptive FEC
Shimizu, K., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3036-3046 11 p.研究成果: Article
Error correction
Error Correction
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Reconfigurable Systems
High-level power optimization based on thread partitioning
Uchida, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2004 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3075-3082 8 p.研究成果: Article
Thread
Partitioning
Optimization
Networks (circuits)
High-level Synthesis
2003
A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories
Togawa, N., Totsuka, T., Wakui, T., Yanagisawa, M. & Ohtsuki, T., 2003 5, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 5, p. 1082-1092 11 p.研究成果: Article
Associative storage
Software System
Hardware
Application programs
Memory Function
2
引用
(Scopus)
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions
Togawa, N., Tachikake, K., Miyaoka, Y., Yanagisawa, M. & Ohtsuki, T., 2003 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3218-3224 7 p.研究成果: Article
Hardware/software Partitioning
Hardware
Unit
Timing
Configuration
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions
Togawa, N., Kasahara, K., Miyaoka, Y., Choi, J., Yanagisawa, M. & Ohtsuki, T., 2003 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 12, p. 3099-3109 11 p.研究成果: Article
Simulator
Simulators
Generator
Hardware
Application programs
2002
A high-level energy-optimizing algorithm for system VLSIs based on area/time/power estimation
Noda, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2655-2666 12 p.研究成果: Article
Energy Levels
Electron energy levels
Energy
High-level Synthesis
Delay Time
3
引用
(Scopus)
An algorithm and a flexible architecture for fast block-matching motion estimation
Choi, J., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2603-2611 9 p.研究成果: Article
Block Matching
Motion Estimation
Motion estimation
Hardware Architecture
Computer hardware description languages
4
引用
(Scopus)
High-level area/delay/power estimation for low power system VLSIs with gated clocks
Noda, S., Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2002 4, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 4, p. 827-834 8 p.研究成果: Article
Power System
Power Consumption
Clocks
Electric power utilization
High-level Synthesis
2001
1
引用
(Scopus)
An area/time optimizing algorithm in high-level synthesis of control-based hardwares
Togawa, N., Ienaga, M., Yanagisawa, M. & Ohsuki, T., 2001 5, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 5, p. 1166-1176 11 p.研究成果: Article
High-level Synthesis
Hardware
Application programs
Graph in graph theory
Hardware Architecture
A new hardware/software partitioning algorithm for DSP processor cores with two types of register files
Togawa, N., Sakurai, T., Yanagisawa, M. & Ohsuki, T., 2001 11, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2802-2807 6 p.研究成果: Article
Hardware/software Partitioning
Hardware
Unit
Digital Signal Processor
Digital signal processors
4
引用
(Scopus)
Area and delay estimation in hardware/software cosynthesis for digital signal processor cores
Togawa, N., Kataoka, Y., Miyaoka, Y., Yanagisawa, M. & Ohsuki, T., 2001 11, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E84-A, 11, p. 2639-2647 9 p.研究成果: Article
Delay Estimation
Digital Signal Processor
Digital signal processors
Hardware
Software
2000
9
引用
(Scopus)
A hardware/software cosynthesis system for digital signal processor cores with two types of register files
Togawa, N., Yanagisawa, M. & Ohtsuki, T., 2000, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 3, p. 442-451 10 p.研究成果: Article
Digital Signal Processor
Digital signal processors
Digital signal processing
Application programs
Software System
1
引用
(Scopus)
CAM processor synthesis based on behavioral descriptions
Togawa, N., Wakui, T., Yoden, T., Terajima, M., Yanagisawa, M. & Ohtsuki, T., 2000 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E83-A, 12, p. 2464-2473 10 p.研究成果: Article
Associative storage
Synthesis
Application programs
Unit
Memory Function
1999
1
引用
(Scopus)
A depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured LUTs
Togawa, N., Ara, K., Yanagisawa, M. & Ohtsuki, T., 1999, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 3, p. 473-481 9 p.研究成果: Article
Logic
Boolean Networks
Minimise
Table lookup
Look-up Table
16
引用
(Scopus)
A hard ware/S oft ware cosynthesis system for digital signal processor cores
Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1999, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 11, p. 2325-2327 3 p.研究成果: Article
Digital Signal Processor
Digital signal processors
Application programs
kernel
Computer hardware
A simultaneous placement and global routing algorithm for FPGAs with power optimization
Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1999 2, ： : Journal of Circuits, Systems and Computers. 9, 1-2, p. 99-112 14 p.研究成果: Article
Routing algorithms
Field programmable gate arrays (FPGA)
Electric power utilization
Networks (circuits)
1998
A fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis
Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1998, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 6, p. 1231-1241 11 p.研究成果: Article
Scheduling algorithms
Scheduling Algorithm
Fast Algorithm
Synthesis
Connectivity
A high-level synthesis system for digital signal processing based on data-flow graph enumeration
Togawa, N., Hisakl, T., Yanagisawa, M. & Ohtsuku, T., 1998, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2563-2575 13 p.研究成果: Article
Data flow graphs
High-level Synthesis
Flow Graphs
Digital signal processing
Data Flow
An FPGA layout reconfiguration algorithm based on global routes for engineering changes in system design specifications
Togawa, N., Hagi, K., Yanagisawa, M. & Ohtsuki, T., 1998, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 5, p. 873-884 12 p.研究成果: Article
Table lookup
Look-up Table
Reconfiguration
Field Programmable Gate Array
System Design
7
引用
(Scopus)
Maple-opt: A performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGA's
Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1998, ： : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17, 9, p. 803-818 16 p.研究成果: Article
Routing algorithms
Field programmable gate arrays (FPGA)
Networks (circuits)
1997
3
引用
(Scopus)
A circuit partitioning algorithm with path delay constraints for multi-FPGA systems
Togawa, N., 1997, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E80-A, 3, p. 494-505 12 p.研究成果: Article
Field Programmable Gate Array
Critical Path
Field programmable gate arrays (FPGA)
Partitioning
Path
A performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems
Togawa, N., Sato, M. & Ohtsuki, T., 1997 10, ： : Journal of Circuits, Systems and Computers. 7, 5, p. 373-393 21 p.研究成果: Article
Field programmable gate arrays (FPGA)
Networks (circuits)
Fast scheduling and allocation algorithms for entropy CODEC
Suzuki, K., Togawa, N., Sato, M. & Ohtsuki, T., 1997, ： : IEICE Transactions on Information and Systems. E80-D, 10, p. 982-992 11 p.研究成果: Article
Flow graphs
Entropy
Scheduling
Scheduling algorithms
Merging
1996
A simultaneous technology mapping, placement, and global routing algorithm for fpgas with path delay constraints
Togawa, N., Sato, M. & Ohtsuki, T., 1996, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E79-A, 3, p. 321-329 9 p.研究成果: Article
Routing algorithms
Routing Algorithm
Field Programmable Gate Array
Placement
Path
3
引用
(Scopus)
Simultaneous placement and global routing for transport-processing FPGA layout
Togawa, N., Sato, M. & Ohtsuki, T., 1996, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E79-A, 12, p. 2140-2149 10 p.研究成果: Article
Field Programmable Gate Array
Placement
Table lookup
Field programmable gate arrays (FPGA)
Layout
1995
2
引用
(Scopus)
Circuit partitioning algorithm with replication capability for multi-FPGA systems
Togawa, N., Sato, M. & Ohtsuki, T., 1995 12, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E78-A, 12, p. 1765-1776 12 p.研究成果: Article
Field Programmable Gate Array
Replication
Field programmable gate arrays (FPGA)
Partitioning
Chip