年別の研究成果
年別の研究成果
- 100 - 113 / 113 件
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1999
A hard ware/S oft ware cosynthesis system for digital signal processor cores
Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1999 1 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E82-A, 11, p. 2325-2327 3 p.研究成果 › 査読
17 被引用数 (Scopus) -
A simultaneous placement and global routing algorithm for FPGAs with power optimization
Togawa, N., Ukai, K., Yanagisawa, M. & Ohtsuki, T., 1999 1 1, In: Journal of Circuits, Systems and Computers. 9, 1-2, p. 99-112 14 p.研究成果 › 査読
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1998
A fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis
Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1998, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 6, p. 1231-1241 11 p.研究成果 › 査読
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A high-level synthesis system for digital signal processing based on data-flow graph enumeration
Togawa, N., Hisakl, T., Yanagisawa, M. & Ohtsuku, T., 1998 1 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 12, p. 2563-2575 13 p.研究成果: Article › 査読
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An FPGA layout reconfiguration algorithm based on global routes for engineering changes in system design specifications
Togawa, N., Hagi, K., Yanagisawa, M. & Ohtsuki, T., 1998 1 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E81-A, 5, p. 873-884 12 p.研究成果 › 査読
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Maple-opt: A performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGA's
Togawa, N., Yanagisawa, M. & Ohtsuki, T., 1998, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17, 9, p. 803-818 16 p.研究成果 › 査読
7 被引用数 (Scopus) -
1997
A circuit partitioning algorithm with path delay constraints for multi-FPGA systems
Togawa, N., 1997 1 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E80-A, 3, p. 494-505 12 p.研究成果 › 査読
3 被引用数 (Scopus) -
A performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems
Togawa, N., Sato, M. & Ohtsuki, T., 1997 10, In: Journal of Circuits, Systems and Computers. 7, 5, p. 373-393 21 p.研究成果 › 査読
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Fast scheduling and allocation algorithms for entropy CODEC
Suzuki, K., Togawa, N., Sato, M. & Ohtsuki, T., 1997 1 1, In: IEICE Transactions on Information and Systems. E80-D, 10, p. 982-992 11 p.研究成果 › 査読
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1996
A simultaneous technology mapping, placement, and global routing algorithm for fpgas with path delay constraints
Togawa, N., Sato, M. & Ohtsuki, T., 1996 1 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E79-A, 3, p. 321-329 9 p.研究成果 › 査読
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Simultaneous placement and global routing for transport-processing FPGA layout
Togawa, N., Sato, M. & Ohtsuki, T., 1996 1 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E79-A, 12, p. 2140-2149 10 p.研究成果 › 査読
3 被引用数 (Scopus) -
1995
Circuit partitioning algorithm with replication capability for multi-FPGA systems
Togawa, N., Sato, M. & Ohtsuki, T., 1995 12 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E78-A, 12, p. 1765-1776 12 p.研究成果: Article › 査読
2 被引用数 (Scopus) -
1994
Maple: A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays
Togawa, N., Sato, M. & Ohtsuki, T., 1994 12 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E77-A, 12, p. 2028-2038 11 p.研究成果 › 査読