• 351 引用
  • 11 h指数
1982 …2019

Research output per year

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

  • 351 引用
  • 11 h指数
  • 51 Conference contribution
  • 45 Article
  • 1 Conference article
2019

A Radix-4 Partial Product Generation-Based Approximate Multiplier for High-speed and Low-power Digital Signal Processing

Sun, X., Guo, Y., Liu, Z. & Kimura, S., 2019 1 17, 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc., p. 777-780 4 p. 8617854. (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018).

研究成果: Conference contribution

Design of Power and Area Efficient Lower-Part-OR Approximate Multiplier

Guo, Y., Sun, H. & Kimura, S., 2019 2 22, Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., p. 2110-2115 6 p. 8650108. (IEEE Region 10 Annual International Conference, Proceedings/TENCON; 巻数 2018-October).

研究成果: Conference contribution

Energy-Efficient and High Performance Approximate Multiplier Using Compressors Based on Input Reordering

Liu, Z., Guo, Y., Sun, X. & Kimura, S., 2019 2 22, Proceedings of TENCON 2018 - 2018 IEEE Region 10 Conference. Institute of Electrical and Electronics Engineers Inc., p. 545-550 6 p. 8650340. (IEEE Region 10 Annual International Conference, Proceedings/TENCON; 巻数 2018-October).

研究成果: Conference contribution

Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors

Guo, Y., Sun, H., Guo, L. & Kimura, S., 2019 1 8, 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc., p. 291-294 4 p. 8605570. (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018).

研究成果: Conference contribution

2 引用 (Scopus)
2018

Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme

Sun, H., Cheng, Z., Gharehbaghi, A. M., Kimura, S. & Fujita, M., 2018 1 1, (Accepted/In press) : : IEEE Transactions on Circuits and Systems I: Regular Papers.

研究成果: Article

7 引用 (Scopus)

A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC

Zhou, J., Zhou, D., Zhang, S., Kimura, S. & Goto, S., 2018 2 1, : : IEEE Transactions on Circuits and Systems for Video Technology. 28, 2, p. 556-560 5 p., 7577726.

研究成果: Article

Embedded Frame Compression for Energy-Efficient Computer Vision Systems

Guo, L., Zhou, D., Zhou, J. & Kimura, S., 2018 4 26, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 巻 2018-May. 8351483

研究成果: Conference contribution

1 引用 (Scopus)

Lossy Compression for Embedded Computer Vision Systems

Guo, L., Zhou, D., Zhou, J., Kimura, S. & Goto, S., 2018 7 3, (Accepted/In press) : : IEEE Access.

研究成果: Article

3 引用 (Scopus)

Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA

Zhang, Z., Zhou, D., Wang, S. & Kimura, S., 2018 2 20, ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., 巻 2018-January. p. 184-189 6 p.

研究成果: Conference contribution

1 引用 (Scopus)

Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression

Guo, L., Zhou, D., Zhou, J. & Kimura, S., 2018 4 26, 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 巻 2018-May. 8351094

研究成果: Conference contribution

Sparse ternary connect: Convolutional neural networks using ternarized weights with enhanced sparsity

Jin, C., Sun, H. & Kimura, S., 2018 2 20, ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., 巻 2018-January. p. 190-195 6 p.

研究成果: Conference contribution

2 引用 (Scopus)

Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging

Ibrahim, A., Zhang, S., Angiolini, F., Arditi, M., Kimura, S., Goto, S., Thiran, J. P. & De Micheli, G., 2018 6 1, (Accepted/In press) : : IEEE Transactions on Biomedical Circuits and Systems.

研究成果: Article

1 引用 (Scopus)
2017

A 7-Die 3D Stacked 3840 × 2160@120 fps motion estimation processor

Zhang, S., Zhou, J., Zhou, D., Kimura, S. & Goto, S., 2017 3 1, : : IEICE Transactions on Electronics. E100C, 3, p. 223-231 9 p.

研究成果: Article

2 引用 (Scopus)

A low-cost approximate 32-point transform architecture

Sun, H., Cheng, Z., Gharehbaghi, A. M., Kimura, S. & Fujita, M., 2017 9 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050263

研究成果: Conference contribution

1 引用 (Scopus)

Effective write-reduction method for MLC non-volatile memory

Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2017 9 25, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050699

研究成果: Conference contribution

Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC

Sun, H., Zhou, D., Hu, L., Kimura, S. & Goto, S., 2017 11 1, : : IEEE Transactions on Multimedia. 19, 11, p. 2375-2390 16 p., 7918540.

研究成果: Article

3 引用 (Scopus)

Optimization of area and power in multi-mode power gating scheme for static memory elements

Su, X. & Kimura, S., 2017 1 3, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., p. 214-217 4 p. 7803936

研究成果: Conference contribution

Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering

Yang, F., Lin, M., Sun, H. & Kimura, S., 2017 9 27, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017. Institute of Electrical and Electronics Engineers Inc., 巻 2017-August. p. 1200-1203 4 p. 8053144

研究成果: Conference contribution

2016

14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications

Zhou, D., Wang, S., Sun, H., Zhou, J., Zhu, J., Zhao, Y., Zhou, J., Zhang, S., Kimura, S., Yoshimura, T. & Goto, S., 2016 2 23, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 巻 59. p. 266-268 3 p. 7418009

研究成果: Conference contribution

16 引用 (Scopus)
1 引用 (Scopus)

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design

Zhou, D., Wang, S., Sun, H., Zhou, J., Zhu, J., Zhao, Y., Zhou, J., Zhang, S., Kimura, S., Yoshimura, T. & Goto, S., 2016 11 4, (Accepted/In press) : : IEEE Journal of Solid-State Circuits.

研究成果: Article

11 引用 (Scopus)

CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks

Han, X., Zhou, D., Wang, S. & Kimura, S., 2016 11 22, Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016. Institute of Electrical and Electronics Engineers Inc., p. 320-327 8 p. 7753296

研究成果: Conference contribution

18 引用 (Scopus)

Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems

Guo, L., Zhou, D., Kimura, S. & Goto, S., 2016 9 22, 2016 IEEE International Conference on Multimedia and Expo Workshop, ICMEW 2016. Institute of Electrical and Electronics Engineers Inc., 7574759

研究成果: Conference contribution

1 引用 (Scopus)

Merge mode based fast inter prediction for HEVC

Cheng, Z., Sun, H., Zhou, D. & Kimura, S., 2016 4 21, 2015 Visual Communications and Image Processing, VCIP 2015. Institute of Electrical and Electronics Engineers Inc., 7457826

研究成果: Conference contribution

1 引用 (Scopus)

Power-efficient and slew-aware three dimensional gated clock tree synthesis

Lin, M., Sun, H. & Kimura, S., 2016 11 22, 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Institute of Electrical and Electronics Engineers Inc., 7753535

研究成果: Conference contribution

5 引用 (Scopus)
2015

A bit-write reduction method based on error-correcting codes for non-volatile memories

Tawada, M., Kimura, S., Yanagisawa, M. & Togawa, N., 2015 3 11, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 496-501 6 p. 7059055

研究成果: Conference contribution

5 引用 (Scopus)

An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder

Sun, H., Zhou, D., Zhu, J., Kimura, S. & Goto, S., 2015 2 27, 2014 IEEE Visual Communications and Image Processing Conference, VCIP 2014. Institute of Electrical and Electronics Engineers Inc., p. 197-200 4 p. 7051538

研究成果: Conference contribution

6 引用 (Scopus)

An independent bandwidth reduction device for HEVC VLSI video system

Zhu, J., Guo, L., Zhou, D., Kimura, S. & Goto, S., 2015 7 27, Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 巻 2015-July. p. 609-612 4 p. 7168707

研究成果: Conference contribution

4 引用 (Scopus)
2 引用 (Scopus)

Hardware-oriented rate-distortion optimization algorithm for HEVC intra-frame encoder

Hu, L., Sun, H., Zhou, D. & Kimura, S., 2015 7 28, 2015 IEEE International Conference on Multimedia and Expo Workshops, ICMEW 2015. Institute of Electrical and Electronics Engineers Inc., 7169808

研究成果: Conference contribution

3 引用 (Scopus)

Low-power motion estimation processor with 3D stacked memory

Zhang, S., Zhou, J., Zhou, D., Kimura, S. & Goto, S., 2015 7 1, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1431-1441 11 p.

研究成果: Article

1 引用 (Scopus)
2014
2 引用 (Scopus)

Fast SAO estimation algorithm and its VLSI architecture

Zhu, J., Zhou, D., Kimura, S. & Goto, S., 2014 1 28, 2014 IEEE International Conference on Image Processing, ICIP 2014. Institute of Electrical and Electronics Engineers Inc., p. 1278-1282 5 p. 7025255

研究成果: Conference contribution

6 引用 (Scopus)

Foreword: Special section on VLSI design and CAD algorithms

Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T. および17人, Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S. I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M. & Watanabe, T., 2014 12 1, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, p. 2366 1 p.

研究成果: Article

2013
11 引用 (Scopus)

Controlling-value-based power gating considering controllability propagation and power-off probability

Du, Z., Jin, Y. & Kimura, S., 2013, Proceedings of International Conference on ASIC. IEEE Computer Society, 6811909

研究成果: Conference contribution

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Matsuno, S., Tawada, M., Yanagisawa, M., Kimura, S., Togawa, N. & Sugibayashi, T., 2013, Proceedings of International Conference on ASIC. IEEE Computer Society, 6811826

研究成果: Conference contribution

1 引用 (Scopus)
2012
1 引用 (Scopus)
2 引用 (Scopus)
2011

Comparison of optimized multi-stage clock gating with structural gating approach

Man, X. & Kimura, S., 2011, IEEE Region 10 Annual International Conference, Proceedings/TENCON. p. 651-656 6 p. 6129188

研究成果: Conference contribution

7 引用 (Scopus)

High-parallel LDPC decoder with power gating design

Cui, Y., Peng, X., Jin, Y., Liu, P., Kimura, S. & Goto, S., 2011, Proceedings of International Conference on ASIC. p. 21-24 4 p. 6157112

研究成果: Conference contribution

Multi-operand adder synthesis targeting FPGAs

Matsunaga, T., Kimura, S. & Matsunaga, Y., 2011 12, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 12, p. 2579-2586 8 p.

研究成果: Article

10 引用 (Scopus)

Multi-stage power gating based on controlling values of logic gates

Jin, Y. & Kimura, S., 2011, Proceedings of International Conference on ASIC. p. 79-82 4 p. 6157127

研究成果: Conference contribution

Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs

Matsunaga, T., Kimura, S. & Matsunaga, Y., 2011, Proceedings of the International Symposium on Low Power Electronics and Design. p. 217-222 6 p. 5993639

研究成果: Conference contribution

13 引用 (Scopus)
2010

Multi-operand adder synthesis on FPGAs using generalized parallel counters

Matsunaga, T., Kimura, S. & Matsunaga, Y., 2010, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 337-342 6 p. 5419871

研究成果: Conference contribution

8 引用 (Scopus)
2 引用 (Scopus)