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研究成果 1982 2019

  • 340 引用
  • 10 h指数
  • 51 Conference contribution
  • 46 Article
  • 1 Conference article
フィルター
Article
2018
4 引用 (Scopus)

Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme

Sun, H., Cheng, Z., Gharehbaghi, A. M., Kimura, S. & Fujita, M., 2018 1 1, (Accepted/In press) : : IEEE Transactions on Circuits and Systems I: Regular Papers.

研究成果: Article

Discrete cosine transforms
Adders
Image coding
Signal processing
Electric power utilization

A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC

Zhou, J., Zhou, D., Zhang, S., Kimura, S. & Goto, S., 2018 2 1, : : IEEE Transactions on Circuits and Systems for Video Technology. 28, 2, p. 556-560 5 p., 7577726.

研究成果: Article

Bins
Clocks
Image coding
Decoding
Entropy
2 引用 (Scopus)

Lossy Compression for Embedded Computer Vision Systems

Guo, L., Zhou, D., Zhou, J., Kimura, S. & Goto, S., 2018 7 3, (Accepted/In press) : : IEEE Access.

研究成果: Article

Computer vision
Data storage equipment
Energy utilization
Differential pulse code modulation
Hardware

Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging

Ibrahim, A., Zhang, S., Angiolini, F., Arditi, M., Kimura, S., Goto, S., Thiran, J. P. & De Micheli, G., 2018 6 1, (Accepted/In press) : : IEEE Transactions on Biomedical Circuits and Systems.

研究成果: Article

Ultrasonics
Imaging techniques
Image sensors
Field programmable gate arrays (FPGA)
Telemedicine
2017

A 7-Die 3D Stacked 3840 × 2160@120 fps motion estimation processor

Zhang, S., Zhou, J., Zhou, D., Kimura, S. & Goto, S., 2017 3 1, : : IEICE Transactions on Electronics. E100C, 3, p. 223-231 9 p.

研究成果: Article

Motion estimation
Data storage equipment
Memory architecture
Silicon
Clocks
2 引用 (Scopus)
Coding
Prediction
Unit
Average-case Complexity
Early Termination
Compression
Optimization
Traffic
Data storage equipment
External Memory
3 引用 (Scopus)

Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC

Sun, H., Zhou, D., Hu, L., Kimura, S. & Goto, S., 2017 11 1, : : IEEE Transactions on Multimedia. 19, 11, p. 2375-2390 16 p., 7918540.

研究成果: Article

Image coding
Throughput
Hardware
Logic gates
Cost functions
2016
1 引用 (Scopus)
VLSI Architecture
Inverse transforms
Quantization
Transform
Data storage equipment
11 引用 (Scopus)

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design

Zhou, D., Wang, S., Sun, H., Zhou, J., Zhu, J., Zhao, Y., Zhou, J., Zhang, S., Kimura, S., Yoshimura, T. & Goto, S., 2016 11 4, (Accepted/In press) : : IEEE Journal of Solid-State Circuits.

研究成果: Article

Image coding
Pipelines
Throughput
Data storage equipment
Energy efficiency
2015
2 引用 (Scopus)
Code Generation
Data storage equipment
Error-correcting Codes
Energy
Static random access storage
1 引用 (Scopus)

Low-power motion estimation processor with 3D stacked memory

Zhang, S., Zhou, J., Zhou, D., Kimura, S. & Goto, S., 2015 7 1, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1431-1441 11 p.

研究成果: Article

Motion Estimation
Motion estimation
Die
Data storage equipment
Image coding
2014
2 引用 (Scopus)
Video Coding
Estimation Algorithms
Image coding
High Efficiency
Encoding

Foreword: Special section on VLSI design and CAD algorithms

Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T. および17人, Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S. I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M. & Watanabe, T., 2014 12 1, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, p. 2366 1 p.

研究成果: Article

2013
10 引用 (Scopus)
Compressor
Adders
Compressors
Synthesis
Inductive logic programming (ILP)
Signal Control
Clustering algorithms
Clustering Algorithm
Optimization
Power Method
Flip flop circuits
State Transition
Flip
Clocks
Electric power utilization
2012
1 引用 (Scopus)
Integer Linear Programming
Linear programming
Clocks
Signal Control
Optimization
2 引用 (Scopus)
Combinatorial circuits
Electric power utilization
Power Consumption
Optimization
Delay circuits
2011
9 引用 (Scopus)

Multi-operand adder synthesis targeting FPGAs

Matsunaga, T., Kimura, S. & Matsunaga, Y., 2011 12, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 12, p. 2579-2586 8 p.

研究成果: Article

Adders
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Synthesis
Application specific integrated circuits
2010
2 引用 (Scopus)
Circuit Switching
Sequential circuits
Signal Control
Clocks
Optimization
2009
Prototyping
Assertion
Field Programmable Gate Array
Shift registers
Automata
Adders
Thermodynamic properties
Dynamic programming
Costs
Binary decision diagrams

Message from technical program committee

Tsay, R. S. & Kimura, S., 2009, : : Unknown Journal. 4796419.

研究成果: Article

4 引用 (Scopus)
Heuristic algorithms
Heuristic algorithm
Sleep
Count
Power Method
VLSI Design
Computer aided design
2008
3 引用 (Scopus)
Multithreading
Thread
Pipelines
Clocks
Throughput
1 引用 (Scopus)
Systolic Array
Systolic arrays
Matrix multiplication
Two Dimensions
Hexagon
2006
3 引用 (Scopus)
High-level Synthesis
Nonlinear programming
Nonlinear Programming
Optimization Methods
Hardware
Symbolic Model Checking
Model checking
Coverage
Hardware
Perturbation
2 引用 (Scopus)
Data compression
Data Compression
Coding
Networks (circuits)
Encoding

Special section on VLSI Design and CAD Algorithms

Onodera, H., Ikeda, M., Ishihara, T., Isshiki, T., Inoue, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kuga, M., Kurokawa, A., Sato, T., Shibuya, T., Shiraishi, Y., Takagi, K., Takahashi, A., Takeuchi, Y., Togawa, N., Tomiyama, H. および10人, Nakamura, Y., Hamaguchi, K., Miura, Y., Minato, S. I., Yamaguchi, R., Yamada, M., Yuminaka, Y., Watanabe, T., Hashimoto, M. & Miyazaki, M., 2006 12, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3377 1 p.

研究成果: Article

VLSI Design
Computer aided design
2005
VLSI Design
Computer aided design
2004
Data compression
Data Compression
Glossaries
Slice
Compression
2003
Linear Feedback Shift Register
Seed
Grouping
ROM
Simulated annealing
1 引用 (Scopus)
High-level Synthesis
Fractional Parts
Fixed point
Optimization
High level languages
2002

Look up table compaction based on folding of logic functions

Kimura, S., Ishii, A., Horiyama, T., Nakanishi, M., Kajihara, H. & Watanabe, K., 2002 12, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2701-2707 7 p.

研究成果: Article

Compaction
Look-up Table
Folding
Logic
Adders
2000
4 引用 (Scopus)
Simplification
Insertion
Cycle
Path
Networks (circuits)
Simplification
Heuristics
Logic
Data storage equipment
Combinatorial circuits
1999
3 引用 (Scopus)
Transistors
Logic
Logic Synthesis
Boolean functions
Optimization
5 引用 (Scopus)
Hardware
Synthesis
Compiler
High level languages
Networks (circuits)
5 引用 (Scopus)
Hardware
Synthesis
Compiler
High level languages
Networks (circuits)
1998
2 引用 (Scopus)
Path Analysis
Sequential circuits
Clocks
Timing
Logic
1993

Preciseness of discrete time verification

Kimura, S., Tsubota, S. & Haneda, H., 1993 10, : : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E76-A, 10, p. 1755-1756 2 p.

研究成果: Article

Logic circuits
Time delay
Discrete-time
Unit
Delay Time
1987
Input Constraints
Logic circuits
Logic
Specification
Specifications