Takashi Ohsawa

2022

A loadless 4T SRAM powered by gate leakage current with a high tolerance for fluctuations in device parameters

Zhu, Y. & Ohsawa, T., 2022, In: Japanese journal of applied physics. 61, SC1053.

研究成果: Article › 査読

2021

Compact model of magnetic tunnel junctions for SPICE simulation based on switching probability

Liu, H. & Ohsawa, T., 2021 3月 1, In: IEICE Transactions on Electronics. E104C, 3, p. 121-127 7 p.

研究成果: Article › 査読

2020

Array design of high-density emerging memories making clamped bit-line sense amplifier compatible with dummy cell average read scheme

Zhang, Z. & Ohsawa, T., 2020 8月, In: IEICE Transactions on Electronics. 103, 8, p. 372-380 9 p.

研究成果: Article › 査読

Co-Design of Binary Processing in Memory ReRAM Array and DNN model optimization algorithm

Guan, Y. & Ohsawa, T., 2020 11月 1, In: IEICE Transactions on Electronics. 103, 11, p. 685-692 8 p.

研究成果: Article › 査読

1 被引用数 (Scopus)

2018

A new read scheme for high-density emerging memories

Ohsawa, T., 2018 6月, In: IEICE Transactions on Electronics. E101C, 6, p. 423-429 7 p.

研究成果: Article › 査読

1 被引用数 (Scopus)

2015

Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation

Koike, H., Ohsawa, T., Miura, S., Honjo, H., Ikeda, S., Hanyu, T., Ohno, H. & Endoh, T., 2015 4月 1, In: Japanese journal of applied physics. 54, 4, 04DE08.

研究成果: Article › 査読

7 被引用数 (Scopus)

2014

A two-transistor bootstrap type selective device for spin-transfer-torque magnetic tunnel junctions

Ohsawa, T., Ikeda, S., Hanyu, T., Ohno, H. & Endoh, T., 2014 4月, In: Japanese journal of applied physics. 53, 4 SPEC. ISSUE, 04ED03.

研究成果: Article › 査読

3 被引用数 (Scopus)

Power reduction by power gating in differential pair type spin-transfer-torque magnetic random access memories for low-power nonvolatile cache memories

Ohsawa, T., Ikeda, S., Hanyu, T., Ohno, H. & Endoh, T., 2014 4月, In: Japanese journal of applied physics. 53, 4 SPEC. ISSUE, 04ED04.

研究成果: Article › 査読

6 被引用数 (Scopus)

Trend of tunnel magnetoresistance and variation in threshold voltage for keeping data load robustness of metal-oxide-semiconductor/magnetic tunnel junction hybrid latches

Ohsawa, T., Ikeda, S., Hanyu, T., Ohno, H. & Endoh, T., 2014 5月 7, In: Journal of Applied Physics. 115, 17, 17C728.

研究成果: Article › 査読

12 被引用数 (Scopus)

Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell

Koike, H., Ohsawa, T., Miura, S., Honjo, H., Ikeda, S., Hanyu, T., Ohno, H. & Endoh, T., 2014 4月, In: Japanese journal of applied physics. 53, 4 SPEC. ISSUE, 04ED13.

研究成果: Article › 査読

9 被引用数 (Scopus)

2013

A 1 Mb nonvolatile embedded memory using 4T2MTJ cell with 32 b fine-grained power gating scheme

Ohsawa, T., Koike, H., Miura, S., Honjo, H., Kinoshita, K., Ikeda, S., Hanyu, T., Ohno, H. & Endoh, T., 2013, In: IEEE Journal of Solid-State Circuits. 48, 6, p. 1511-1520 10 p., 6495490.

研究成果: Article › 査読

65 被引用数 (Scopus)

2012

High-density and low-power nonvolatile static random access memory using spin-transfer-torque magnetic tunnel junction

Ohsawa, T., Iga, F., Ikeda, S., Hanyu, T., Ohno, H. & Endoh, T., 2012 2月 1, In: Japanese journal of applied physics. 51, 2 PART 2, 02BD01.

研究成果: Article › 査読

29 被引用数 (Scopus)

Low power nonvolatile counter unit with fine-grained power gating

Togashi, S., Ohsawa, T. & Endoh, T., 2012 5月, In: IEICE Transactions on Electronics. E95-C, 5, p. 854-859 6 p.

研究成果: Article › 査読

Nonvolatile low power 16-bit/32-bit magnetic tunnel junction based binary counter and its scaling

Togashi, S., Ohsawa, T. & Endoh, T., 2012 2月 1, In: Japanese journal of applied physics. 51, 2 PART 2, 02BE07.

研究成果: Article › 査読

5 被引用数 (Scopus)

2011

Generation of accurate reference current for data sensing in high-density memories by averaging multiple Pairs of dummy cells

Ohsawa, T., Hatsuda, K., Fujita, K., Matsuoka, F. & Higashi, T., 2011 9月, In: IEEE Journal of Solid-State Circuits. 46, 9, p. 2148-2157 10 p., 5783952.

研究成果: Article › 査読

7 被引用数 (Scopus)

2010

Reduction of bipolar disturb of floating-body cell (FBC) by silicide and thin silicon film formed at source and drain regions

Hamamoto, T., Fukuzumi, Y., Higashi, T., Nakajima, H., Minami, Y., Shino, T., Ohsawa, T. & Nitayama, A., 2010 8月 1, In: IEEE Transactions on Electron Devices. 57, 8, p. 1781-1788 8 p., 5484457.

研究成果: Article › 査読

2009

Autonomous refresh of floating-body cell due to current anomaly of impact ionization

Ohsawa, T., Fukuda, R., Higashi, T., Fujita, K., Matsuoka, F., Shino, T., Furuhashi, H., Minami, Y., Nakajima, H., Hamamoto, T., Watanabe, Y., Nitayama, A. & Furuyama, T., 2009, In: IEEE Transactions on Electron Devices. 56, 10, p. 2302-2311 10 p.

研究成果: Article › 査読

3 被引用数 (Scopus)

Overview and future challenges of floating body RAM (FBRAM) technology for 32 nm technology node and beyond

Hamamoto, T. & Ohsawa, T., 2009 7月, In: Solid-State Electronics. 53, 7, p. 676-683 8 p.

研究成果: Article › 査読

19 被引用数 (Scopus)

2007

A floating-body cell fully compatible with 90-nm CMOS technology node for a 128-Mb SOI DRAM and its scalability

Hamamoto, T., Minami, Y., Shino, T., Kusunoki, N., Nakajima, H., Morikado, M., Yamada, T., Inoh, K., Sakamoto, A., Higashi, T., Fujita, K., Hatsuda, K., Ohsawa, T. & Nitayama, A., 2007 3月, In: IEEE Transactions on Electron Devices. 54, 3, p. 563-571 9 p.

研究成果: Article › 査読

26 被引用数 (Scopus)

2006

Design of a 128-mb SOI DRAM using the floating body cell (FBC)

Ohsawa, T., Fujita, K., Hatsuda, K., Higashi, T., Shino, T., Minami, Y., Nakajima, H., Morikado, M., Inoh, K., Hamamoto, T., Watanabe, S., Fujii, S. & Furuyama, T., 2006 1月, In: IEEE Journal of Solid-State Circuits. 41, 1, p. 135-145 11 p.

研究成果: Article › 査読

13 被引用数 (Scopus)

2005

Operation voltage dependence of memory cell characteristics in fully depleted floating-body cell

Shino, T., Ohsawa, T., Higashi, T., Fujita, K., Kusunoki, N., Minami, Y., Morikado, M., Nakajima, H., Inoh, K., Hamamoto, T. & Nitayama, A., 2005 10月, In: IEEE Transactions on Electron Devices. 52, 10, p. 2220-2225 6 p.

研究成果: Article › 査読

21 被引用数 (Scopus)

2002

Memory design using a one-transistor gain cell on SOI

Ohsawa, T., Fujita, K., Higashi, T., Iwata, Y., Kajiyama, T., Asao, Y. & Sunouchi, K., 2002 11月, In: IEEE Journal of Solid-State Circuits. 37, 11, p. 1510-1522 13 p.

研究成果: Article › 査読

54 被引用数 (Scopus)

1996

A 250 mV bit-line swing scheme for 1-v operating gigabit scale drams

Inaba, T., Takashima, D., Oowaki, Y., Ozaklt, T., Watanabe, S., Ohsawa, T., Ohuchi, K. & Tango, H., 1996 1月 1, In: IEICE Transactions on Electronics. E79-C, 12, p. 1699-1705 7 p.

研究成果: Article › 査読

1991

A 12-MHz Data Cycle 4-Mb DRAM with Pipeline Operation

Kushiyama, N., Watanabe, Y., Ohsawa, T., Muraoka, K., Furuyama, T. & Nagahama, Y., 1991 4月, In: IEEE Journal of Solid-State Circuits. 26, 4, p. 479-483 5 p.

研究成果: Article › 査読

2 被引用数 (Scopus)

1989

A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM’s

Watanabe, Y., Ohsawa, T., Sakurai, K. & Furuyama, T., 1989 8月, In: IEEE Journal of Solid-State Circuits. 24, 4, p. 905-910 6 p.

研究成果: Article › 査読

13 被引用数 (Scopus)

An Experimental 2-bit/Cell Storage DRAM for Macroce11 or Memory-on-Logic Application

Furuyama, T., Ohsawa, T., Watanabe, Y., Muraoka, K., Natori, K., Nagahama, Y., Kimura, T. & Tanaka, H., 1989 4月, In: IEEE Journal of Solid-State Circuits. 24, 2, p. 388-393 6 p.

研究成果: Article › 査読

20 被引用数 (Scopus)

1987

A 60-ns 4-Mbit CMOS DRAM with Built-In Self-Test Function

Ohsawa, T., Furuyama, T., Watanabe, Y., Tanaka, H., Natori, K., Shinozaki, S., Tanaka, T., Yamano, S., Nagahama, Y., Kushiyama, N. & Tsuchida, K., 1987 10月, In: IEEE Journal of Solid-State Circuits. 22, 5, p. 663-668 6 p.

研究成果: Article › 査読

16 被引用数 (Scopus)

A New On-Chip Voltage Converter for Submicrometer High-Density DRAM's

Furuyama, T., Watanabe, Y., Ohsawa, T. & Watanabe, S., 1987 6月, In: IEEE Journal of Solid-State Circuits. 22, 3, p. 437-441 5 p.

研究成果: Article › 査読

24 被引用数 (Scopus)

1986

An Experimental 4-Mbit CMOS DRAM

Furuyama, T., Ohsawa, T., Watanabe, Y., Ishiuchi, H., Watanabe, T., Tanaka, T., Natori, K. & Ozawa, O., 1986 10月, In: IEEE Journal of Solid-State Circuits. 21, 5, p. 605-611 7 p.

研究成果: Article › 査読

25 被引用数 (Scopus)

1983

Azimuthal Current-Neutralization of a Rotational Light Ion Beam by a Plasma

Ohsawa, T. & Kato, T., 1983, In: journal of the physical society of japan. 52, 8, p. 2727-2735 9 p.

研究成果: Article › 査読

Thermodynamic Theory of Light Ion Beam Propagation in a Plasma

Kato, T. & Ohsawa, T., 1983 1月 1, In: journal of the physical society of japan. 52, 8, p. 2720-2726 7 p.

研究成果: Article › 査読

1 被引用数 (Scopus)

1980

Synchronous quenching due to nonlinear mode coupling in beam-plasma system

Ohsawa, T., 1980, In: journal of the physical society of japan. 49, 6, p. 2340-2348 9 p.

研究成果: Article › 査読

2 被引用数 (Scopus)

1979

Theory of the Parametric Oscillation in an Electron Beam-Plasma System

Kato, T., Okazaki, T. & Ohsawa, T., 1979, In: journal of the physical society of japan. 46, 1, p. 277-284 8 p.

研究成果: Article › 査読

1 被引用数 (Scopus)

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