0.1-μm gate-length superconducting FET

T. Nishino, M. Hatano, H. Hasegawa, F. Murai, T. Kure, A. Hiraiwa, K. Yagi, Ushio Kawabe

研究成果: Article

36 引用 (Scopus)

抄録

A superconducting field-effect transistor (FET) with a 0.1-μm-length gate electrode was fabricated and tested at liquid-helium temperature. Two superconducting electrodes (source and drain) were formed on the same Si substrate surface with an oxide-insulated gate electrode by a self-aligned fabrication process. Superconducting current flowing through the semiconductor (Si) between the two superconducting electrodes (Nb) was controlled by a gate-bias voltage.

元の言語English
ページ(範囲)61-63
ページ数3
ジャーナルElectron device letters
10
発行部数2
出版物ステータスPublished - 1989 2
外部発表Yes

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Gates (transistor)
Field effect transistors
Electrodes
Semiconductor materials
Helium
Bias voltage
Oxides
Fabrication
Liquids
Substrates
Temperature

ASJC Scopus subject areas

  • Engineering(all)

これを引用

Nishino, T., Hatano, M., Hasegawa, H., Murai, F., Kure, T., Hiraiwa, A., ... Kawabe, U. (1989). 0.1-μm gate-length superconducting FET. Electron device letters, 10(2), 61-63.

0.1-μm gate-length superconducting FET. / Nishino, T.; Hatano, M.; Hasegawa, H.; Murai, F.; Kure, T.; Hiraiwa, A.; Yagi, K.; Kawabe, Ushio.

:: Electron device letters, 巻 10, 番号 2, 02.1989, p. 61-63.

研究成果: Article

Nishino, T, Hatano, M, Hasegawa, H, Murai, F, Kure, T, Hiraiwa, A, Yagi, K & Kawabe, U 1989, '0.1-μm gate-length superconducting FET', Electron device letters, 巻. 10, 番号 2, pp. 61-63.
Nishino T, Hatano M, Hasegawa H, Murai F, Kure T, Hiraiwa A その他. 0.1-μm gate-length superconducting FET. Electron device letters. 1989 2;10(2):61-63.
Nishino, T. ; Hatano, M. ; Hasegawa, H. ; Murai, F. ; Kure, T. ; Hiraiwa, A. ; Yagi, K. ; Kawabe, Ushio. / 0.1-μm gate-length superconducting FET. :: Electron device letters. 1989 ; 巻 10, 番号 2. pp. 61-63.
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AU - Hatano, M.

AU - Hasegawa, H.

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AU - Kure, T.

AU - Hiraiwa, A.

AU - Yagi, K.

AU - Kawabe, Ushio

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AB - A superconducting field-effect transistor (FET) with a 0.1-μm-length gate electrode was fabricated and tested at liquid-helium temperature. Two superconducting electrodes (source and drain) were formed on the same Si substrate surface with an oxide-insulated gate electrode by a self-aligned fabrication process. Superconducting current flowing through the semiconductor (Si) between the two superconducting electrodes (Nb) was controlled by a gate-bias voltage.

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