TY - JOUR
T1 - 0.15 μm CMOS process for high performance and high reliability
AU - Shimizu, S.
AU - Kuroi, T.
AU - Kobayashi, M.
AU - Yamaguchi, T.
AU - Fujino, T.
AU - Maeda, H.
AU - Tsutsumi, T.
AU - Hirose, Y.
AU - Kusunoki, S.
AU - Inuishi, M.
AU - Tsubouchi, N.
PY - 1994/12/1
Y1 - 1994/12/1
N2 - We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi2/Si interface using Si+ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.
AB - We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi2/Si interface using Si+ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.
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M3 - Conference article
AN - SCOPUS:0028736933
SP - 67
EP - 70
JO - Technical Digest - International Electron Devices Meeting
JF - Technical Digest - International Electron Devices Meeting
SN - 0163-1918
T2 - Proceedings of the 1994 IEEE International Electron Devices Meeting
Y2 - 11 December 1994 through 14 December 1994
ER -