0.15 μm CMOS process for high performance and high reliability

S. Shimizu, T. Kuroi, M. Kobayashi, T. Yamaguchi, T. Fujino, H. Maeda, T. Tsutsumi, Y. Hirose, S. Kusunoki, M. Inuishi, N. Tsubouchi

研究成果: Conference article

12 被引用数 (Scopus)

抄録

We have developed the novel 0.15μm CMOS processes for high performance and high reliability, consisting of mixing the CoSi2/Si interface using Si+ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using those processes, the propagation delay time of 21 psec/stage was obtained for 0.15μm CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.

本文言語English
ページ(範囲)67-70
ページ数4
ジャーナルTechnical Digest - International Electron Devices Meeting
出版ステータスPublished - 1994 12 1
外部発表はい
イベントProceedings of the 1994 IEEE International Electron Devices Meeting - San Francisco, CA, USA
継続期間: 1994 12 111994 12 14

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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