0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica

Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara

研究成果: Article

5 引用 (Scopus)

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A 200-MHz double-data-rate synchronous-DRAM (DDR-SDRAM) was developed. The chip contains a delay-locked loop (DLL) which performs over a wide range of operating conditions. Post-mold-tuning allows precise replica programming. A 200-MHz intra-chip data bus is suitable for DDR operation.

元の言語English
ページ(範囲)1680-1689
ページ数10
ジャーナルIEEE Journal of Solid-State Circuits
35
発行部数11
DOI
出版物ステータスPublished - 2000 11
外部発表Yes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Kuge, S., Kato, T., Furutani, K., Kikuda, S., Mitsui, K., Hamamoto, T., Setogawa, J., Hamade, K., Komiya, Y., Kawasaki, S., Kono, T., Amano, T., Kubo, T., Haraguchi, M., Nakaoka, Y., Akiyama, M., Konishi, Y., Ozaki, H., & Yoshihara, T. (2000). 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. IEEE Journal of Solid-State Circuits, 35(11), 1680-1689. https://doi.org/10.1109/4.881215