100x evolution of video codec chips

Jinjia Zhou, Dajiang Zhou, Satoshi Goto

    研究成果: Conference contribution

    1 被引用数 (Scopus)

    抄録

    In the past two decades, there has been tremendous progress in video compression technologies. Meanwhile, the use of these technologies, along with the ever-increasing demand for emerging ultra-high-definition applications greatly challenges the design of video codec chips, with the extensive requirements on both memory (DRAM) bandwidth and computation power. Besides, the high data dependencies of video coding algorithms restrict the degree of efficient hardware parallelism and pipelining. This paper describes the techniques to realize high-performance video codec chips. Firstly, we introduce various optimization techniques to solve the DRAM traffic issue. Furthermore, the techniques to reduce the computational complexity and alleviate data dependencies are described. The proposed techniques have been implemented in several ASIC video codecs. Experiments show that the DRAM traffic and DRAM access time are reduced by 80% and 90% respectively.

    本文言語English
    ホスト出版物のタイトルISPD 2017 - Proceedings of the 2017 ACM International Symposium on Physical Design
    出版社Association for Computing Machinery
    ページ121-122
    ページ数2
    Part F127197
    ISBN(電子版)9781450346962
    DOI
    出版ステータスPublished - 2017 3 19
    イベント2017 ACM International Symposium on Physical Design, ISPD 2017 - Portland, United States
    継続期間: 2017 3 192017 3 22

    Other

    Other2017 ACM International Symposium on Physical Design, ISPD 2017
    CountryUnited States
    CityPortland
    Period17/3/1917/3/22

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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