1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit

H. Suzuki, H. Takata, H. Shinohara, E. Teraoka, M. Matsuo, T. Yoshida, H. Sato, N. Honda, N. Masui, T. Shimizu

研究成果: Conference contribution

2 引用 (Scopus)

抜粋

1.047GHz synthesizable 2-way VLIW General Purpose DSP core has been developed by 1.2V 90nm CMOS technology. The key technology is to detect saturation from adder's inputs in an ALU and parallelize the saturation check with the adder operation. The proposed saturation anticipator circuit and the logic structure optimization improve DSP's clock frequency by 20.8%. The test chip also runs 0.10uW/MHz at 0.8V low power operation mode.

元の言語English
ホスト出版物のタイトル2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
ページ152-153
ページ数2
出版物ステータスPublished - 2006 12 1
外部発表Yes
イベント2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
継続期間: 2006 6 152006 6 17

出版物シリーズ

名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2006 Symposium on VLSI Circuits, VLSIC
United States
Honolulu, HI
期間06/6/1506/6/17

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • これを引用

    Suzuki, H., Takata, H., Shinohara, H., Teraoka, E., Matsuo, M., Yoshida, T., Sato, H., Honda, N., Masui, N., & Shimizu, T. (2006). 1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit. : 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers (pp. 152-153). [1705355] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).