12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains

Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations within a functional block are compensated by the fine-grained supply voltage (VDD) control to minimize power at fixed clock frequency. In the 40-nm test chips, the layout of a data encryption core is divided into 6x7 voltage domains. Both high VDD (VDDH) and low VDD (VDDL) are supplied to each power domain and either VDDH or VDDL is adaptively selected according to the setup error warning signals generated by canary flip-flops. Compared with the conventional single VDD operation, the proposed FADVC reduced the power by 12% at 1-MHz clock in the measurement.

本文言語English
ホスト出版物のタイトルESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
ページ191-194
ページ数4
DOI
出版ステータスPublished - 2011 12 12
外部発表はい
イベント37th European Solid-State Circuits Conference, ESSCIRC 2011 - Helsinki, Finland
継続期間: 2011 9 122011 9 16

出版物シリーズ

名前European Solid-State Circuits Conference
ISSN(印刷版)1930-8833

Other

Other37th European Solid-State Circuits Conference, ESSCIRC 2011
CountryFinland
CityHelsinki
Period11/9/1211/9/16

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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