1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology

Uroschanit Yodprasit; Kosuke Katayama; Ryuichi Fujimoto; Mizuki Motoyoshi; Minoru Fujishima

doi:10.1109/ISCDG.2013.6656291

1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology

Uroschanit Yodprasit, Kosuke Katayama, Ryuichi Fujimoto, Mizuki Motoyoshi, Minoru Fujishima

研究成果

2 被引用数 (Scopus)

抄録

In this paper, design and characterization of a medium-power power amplifier targeted for short-range wireless communications in W-band frequency are presented. The power amplifier consists of six stages of common-source gain stages biased in class-A mode to maximize the power gain. The matching networks are based on slow-wave transmission lines in order to compact the layout. Fabricated in a 65-nm CMOS process, the power amplifier achieves a maximum power gain of 8.5 dB at 101 GHz and a 3-dB bandwidth of 18 GHz. The power amplifier delivers a saturation power of 7.1 dBm using a 1.2-V supply voltage and consumes 189 mW.

本文言語	English
ホスト出版物のタイトル	2013 IEEE International Semiconductor Conference Dresden - Grenoble
ホスト出版物のサブタイトル	Technology, Design, Packaging, Simulation and Test, ISCDG 2013
DOI	https://doi.org/10.1109/ISCDG.2013.6656291
出版ステータス	Published - 2013
外部発表	はい
イベント	2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013 - Dresden, Germany 継続期間: 2013 9 26 → 2013 9 27

出版物シリーズ

名前	2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013

Other

Other	2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013
国/地域	Germany
City	Dresden
Period	13/9/26 → 13/9/27

ASJC Scopus subject areas

電子工学および電気工学

文献へのアクセス

10.1109/ISCDG.2013.6656291

他のファイルとリンク

引用スタイル

Yodprasit, U., Katayama, K., Fujimoto, R., Motoyoshi, M., & Fujishima, M. (2013). 1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology. In 2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013 [6656291] (2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013). https://doi.org/10.1109/ISCDG.2013.6656291

1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology. / Yodprasit, Uroschanit; Katayama, Kosuke; Fujimoto, Ryuichi; Motoyoshi, Mizuki; Fujishima, Minoru.

2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013. 2013. 6656291 (2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013).

研究成果

Yodprasit, U, Katayama, K, Fujimoto, R, Motoyoshi, M & Fujishima, M 2013, 1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology. in 2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013., 6656291, 2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013, 2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013, Dresden, Germany, 13/9/26. https://doi.org/10.1109/ISCDG.2013.6656291

Yodprasit U, Katayama K, Fujimoto R, Motoyoshi M, Fujishima M. 1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology. In 2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013. 2013. 6656291. (2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013). https://doi.org/10.1109/ISCDG.2013.6656291

Yodprasit, Uroschanit ; Katayama, Kosuke ; Fujimoto, Ryuichi ; Motoyoshi, Mizuki ; Fujishima, Minoru. / 1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology. 2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013. 2013. (2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013).

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abstract = "In this paper, design and characterization of a medium-power power amplifier targeted for short-range wireless communications in W-band frequency are presented. The power amplifier consists of six stages of common-source gain stages biased in class-A mode to maximize the power gain. The matching networks are based on slow-wave transmission lines in order to compact the layout. Fabricated in a 65-nm CMOS process, the power amplifier achieves a maximum power gain of 8.5 dB at 101 GHz and a 3-dB bandwidth of 18 GHz. The power amplifier delivers a saturation power of 7.1 dBm using a 1.2-V supply voltage and consumes 189 mW.",

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1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology

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出版物シリーズ

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