TY - GEN
T1 - 1.2-V 101-GHz W-band power amplifier integrated in a 65-nm CMOS technology
AU - Yodprasit, Uroschanit
AU - Katayama, Kosuke
AU - Fujimoto, Ryuichi
AU - Motoyoshi, Mizuki
AU - Fujishima, Minoru
PY - 2013
Y1 - 2013
N2 - In this paper, design and characterization of a medium-power power amplifier targeted for short-range wireless communications in W-band frequency are presented. The power amplifier consists of six stages of common-source gain stages biased in class-A mode to maximize the power gain. The matching networks are based on slow-wave transmission lines in order to compact the layout. Fabricated in a 65-nm CMOS process, the power amplifier achieves a maximum power gain of 8.5 dB at 101 GHz and a 3-dB bandwidth of 18 GHz. The power amplifier delivers a saturation power of 7.1 dBm using a 1.2-V supply voltage and consumes 189 mW.
AB - In this paper, design and characterization of a medium-power power amplifier targeted for short-range wireless communications in W-band frequency are presented. The power amplifier consists of six stages of common-source gain stages biased in class-A mode to maximize the power gain. The matching networks are based on slow-wave transmission lines in order to compact the layout. Fabricated in a 65-nm CMOS process, the power amplifier achieves a maximum power gain of 8.5 dB at 101 GHz and a 3-dB bandwidth of 18 GHz. The power amplifier delivers a saturation power of 7.1 dBm using a 1.2-V supply voltage and consumes 189 mW.
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U2 - 10.1109/ISCDG.2013.6656291
DO - 10.1109/ISCDG.2013.6656291
M3 - Conference contribution
AN - SCOPUS:84892148209
SN - 9781479912506
T3 - 2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013
BT - 2013 IEEE International Semiconductor Conference Dresden - Grenoble
T2 - 2013 IEEE International Semiconductor Conference Dresden - Grenoble: Technology, Design, Packaging, Simulation and Test, ISCDG 2013
Y2 - 26 September 2013 through 27 September 2013
ER -