A microprocessor with single instruction multiple data (SIMD) stream architecture and as many as 170 media instructions for multimedia embedded systems meet all requirements of embedded systems. The chip employs a two-way superscalar, five stage pipeline, in-order execution design. The chip achieves 2.16 GOPS, satisfying the performance requirement for motion picture experts group (MPEG2) decoding. The floating point multiplier (FMUL) and floating point adder (FADD) execute two 32 b floating point multiply-add operations every clock cycle. This achieves 720 MFLOPS, which satisfies the requirement for 3D computer graphics image processing.
|出版ステータス||Published - 1998|
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