1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications

H. Kubosawa; H. Takahashi; S. Ando; Y. Asada; A. Asato; A. Suga; M. Kimura; N. Higaki; H. Miyake; T. Sato; H. Anbutsu; T. Tsuda; T. Yoshimura; I. Amano; M. Kai; S. Mitarai

1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications

H. Kubosawa^*, H. Takahashi, S. Ando, Y. Asada, A. Asato, A. Suga, M. Kimura, N. Higaki, H. Miyake, T. Sato, H. Anbutsu, T. Tsuda, T. Yoshimura, I. Amano, M. Kai, S. Mitarai

^*この研究の対応する著者

研究成果 › 査読

4 被引用数 (Scopus)

抄録

A microprocessor with single instruction multiple data (SIMD) stream architecture and as many as 170 media instructions for multimedia embedded systems meet all requirements of embedded systems. The chip employs a two-way superscalar, five stage pipeline, in-order execution design. The chip achieves 2.16 GOPS, satisfying the performance requirement for motion picture experts group (MPEG2) decoding. The floating point multiplier (FMUL) and floating point adder (FADD) execute two 32 b floating point multiply-add operations every clock cycle. This achieves 720 MFLOPS, which satisfies the requirement for 3D computer graphics image processing.

本文言語	English
ページ（範囲）	290-291
ページ数	2
ジャーナル	Unknown Journal
出版ステータス	Published - 1998

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

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@article{a009bb5d36154dfcb06b86bea8aed7be,

title = "1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications",

abstract = "A microprocessor with single instruction multiple data (SIMD) stream architecture and as many as 170 media instructions for multimedia embedded systems meet all requirements of embedded systems. The chip employs a two-way superscalar, five stage pipeline, in-order execution design. The chip achieves 2.16 GOPS, satisfying the performance requirement for motion picture experts group (MPEG2) decoding. The floating point multiplier (FMUL) and floating point adder (FADD) execute two 32 b floating point multiply-add operations every clock cycle. This achieves 720 MFLOPS, which satisfies the requirement for 3D computer graphics image processing.",

author = "H. Kubosawa and H. Takahashi and S. Ando and Y. Asada and A. Asato and A. Suga and M. Kimura and N. Higaki and H. Miyake and T. Sato and H. Anbutsu and T. Tsuda and T. Yoshimura and I. Amano and M. Kai and S. Mitarai",

year = "1998",

language = "English",

pages = "290--291",

journal = "Nuclear Physics A",

issn = "0375-9474",

publisher = "Elsevier",

}

TY - JOUR

T1 - 1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications

AU - Kubosawa, H.

AU - Takahashi, H.

AU - Ando, S.

AU - Asada, Y.

AU - Asato, A.

AU - Suga, A.

AU - Kimura, M.

AU - Higaki, N.

AU - Miyake, H.

AU - Sato, T.

AU - Anbutsu, H.

AU - Tsuda, T.

AU - Yoshimura, T.

AU - Amano, I.

AU - Kai, M.

AU - Mitarai, S.

PY - 1998

Y1 - 1998

N2 - A microprocessor with single instruction multiple data (SIMD) stream architecture and as many as 170 media instructions for multimedia embedded systems meet all requirements of embedded systems. The chip employs a two-way superscalar, five stage pipeline, in-order execution design. The chip achieves 2.16 GOPS, satisfying the performance requirement for motion picture experts group (MPEG2) decoding. The floating point multiplier (FMUL) and floating point adder (FADD) execute two 32 b floating point multiply-add operations every clock cycle. This achieves 720 MFLOPS, which satisfies the requirement for 3D computer graphics image processing.

AB - A microprocessor with single instruction multiple data (SIMD) stream architecture and as many as 170 media instructions for multimedia embedded systems meet all requirements of embedded systems. The chip employs a two-way superscalar, five stage pipeline, in-order execution design. The chip achieves 2.16 GOPS, satisfying the performance requirement for motion picture experts group (MPEG2) decoding. The floating point multiplier (FMUL) and floating point adder (FADD) execute two 32 b floating point multiply-add operations every clock cycle. This achieves 720 MFLOPS, which satisfies the requirement for 3D computer graphics image processing.

UR - http://www.scopus.com/inward/record.url?scp=0031706874&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031706874&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0031706874

SP - 290

EP - 291

JO - Nuclear Physics A

JF - Nuclear Physics A

SN - 0375-9474

ER -

1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications

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ASJC Scopus subject areas

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