1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications

H. Kubosawa, H. Takahashi, S. Ando, Y. Asada, A. Asato, A. Suga, M. Kimura, N. Higaki, H. Miyake, T. Sato, H. Anbutsu, T. Tsuda, T. Yoshimura, I. Amano, M. Kai, S. Mitarai

    研究成果: Article

    4 引用 (Scopus)

    抜粋

    A microprocessor with single instruction multiple data (SIMD) stream architecture and as many as 170 media instructions for multimedia embedded systems meet all requirements of embedded systems. The chip employs a two-way superscalar, five stage pipeline, in-order execution design. The chip achieves 2.16 GOPS, satisfying the performance requirement for motion picture experts group (MPEG2) decoding. The floating point multiplier (FMUL) and floating point adder (FADD) execute two 32 b floating point multiply-add operations every clock cycle. This achieves 720 MFLOPS, which satisfies the requirement for 3D computer graphics image processing.

    元の言語English
    ページ(範囲)290-291
    ページ数2
    ジャーナルUnknown Journal
    出版物ステータスPublished - 1998

      フィンガープリント

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    これを引用

    Kubosawa, H., Takahashi, H., Ando, S., Asada, Y., Asato, A., Suga, A., Kimura, M., Higaki, N., Miyake, H., Sato, T., Anbutsu, H., Tsuda, T., Yoshimura, T., Amano, I., Kai, M., & Mitarai, S. (1998). 1.2 W 2.16 GOPS/720 MFLOPS embedded superscalar microprocessor for multimedia applications. Unknown Journal, 290-291.