120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs

Yasushi Terada; Kazuo Kobayashi; Takeshi Nakayama; Masanori Hayashikoshi; Yoshikazu Miyawaki; Natsuo Ajika; Hideaki Arima; Takayuki Matsukawa; Tsutomu Yoshihara

120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs

Yasushi Terada^*, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

^*この研究の対応する著者

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0-μm triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 μm × 8 μm, and the chip is 7.73 mm × 11.83 mm. The device is configured as either 128k × 8 or 64k × 16 by a through-hole mask option. A 120-ns read access time has been achieved. The differential sensing scheme uses an output of the current sense amplifier connected to an unselected memory array as a reference level. The sense amplifier, the clock timing diagram, and the access waveform are shown, and typical process parameters are listed.

本文言語	English
ホスト出版物のタイトル	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
編集者	Anon
出版社	Publ by IEEE
ページ	136-137, 315
巻	32
出版ステータス	Published - 1989
外部発表	はい
イベント	IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) - New York, NY, USA 継続期間: 1989 2月 15 → 1989 2月 17

Other

Other	IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989)
City	New York, NY, USA
Period	89/2/15 → 89/2/17

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

他のファイルとリンク

引用スタイル

120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs. / Terada, Yasushi; Kobayashi, Kazuo; Nakayama, Takeshi; Hayashikoshi, Masanori; Miyawaki, Yoshikazu; Ajika, Natsuo; Arima, Hideaki; Matsukawa, Takayuki; Yoshihara, Tsutomu.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. ed. / Anon. Vol. 32 Publ by IEEE, 1989. p. 136-137, 315.

研究成果: Conference contribution

Terada, Y, Kobayashi, K, Nakayama, T, Hayashikoshi, M, Miyawaki, Y, Ajika, N, Arima, H, Matsukawa, T & Yoshihara, T 1989, 120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs. in Anon (ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 32, Publ by IEEE, pp. 136-137, 315, IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989), New York, NY, USA, 89/2/15.

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abstract = "A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0-μm triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 μm × 8 μm, and the chip is 7.73 mm × 11.83 mm. The device is configured as either 128k × 8 or 64k × 16 by a through-hole mask option. A 120-ns read access time has been achieved. The differential sensing scheme uses an output of the current sense amplifier connected to an unselected memory array as a reference level. The sense amplifier, the clock timing diagram, and the access waveform are shown, and typical process parameters are listed.",

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AU - Terada, Yasushi

AU - Kobayashi, Kazuo

AU - Nakayama, Takeshi

AU - Hayashikoshi, Masanori

AU - Miyawaki, Yoshikazu

AU - Ajika, Natsuo

AU - Arima, Hideaki

AU - Matsukawa, Takayuki

AU - Yoshihara, Tsutomu

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Y1 - 1989

N2 - A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0-μm triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 μm × 8 μm, and the chip is 7.73 mm × 11.83 mm. The device is configured as either 128k × 8 or 64k × 16 by a through-hole mask option. A 120-ns read access time has been achieved. The differential sensing scheme uses an output of the current sense amplifier connected to an unselected memory array as a reference level. The sense amplifier, the clock timing diagram, and the access waveform are shown, and typical process parameters are listed.

AB - A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0-μm triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 μm × 8 μm, and the chip is 7.73 mm × 11.83 mm. The device is configured as either 128k × 8 or 64k × 16 by a through-hole mask option. A 120-ns read access time has been achieved. The differential sensing scheme uses an output of the current sense amplifier connected to an unselected memory array as a reference level. The sense amplifier, the clock timing diagram, and the access waveform are shown, and typical process parameters are listed.

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SP - 136-137, 315

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

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PB - Publ by IEEE

T2 - IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989)

Y2 - 15 February 1989 through 17 February 1989

ER -

120 ns 128k × 8 b/64k × 16 b CMOS EEPROMs

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