抄録
A 1-Mb CMOS EEPROM (electrically erasable and programmable read-only memory) using a 1.0-μm triple-polysilicon, double-metal process is described. To achieve a manufacturable 120-ns 1-Mb EEPROM with a small chip, a memory cell with high current drive, improved differential sensing technique, and error-correcting code (ECC) was developed. The cell size is 3.8 μm × 8 μm, and the chip is 7.73 mm × 11.83 mm. The device is configured as either 128k × 8 or 64k × 16 by a through-hole mask option. A 120-ns read access time has been achieved. The differential sensing scheme uses an output of the current sense amplifier connected to an unselected memory array as a reference level. The sense amplifier, the clock timing diagram, and the access waveform are shown, and typical process parameters are listed.
本文言語 | English |
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ホスト出版物のタイトル | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
編集者 | Anon |
出版社 | Publ by IEEE |
ページ | 136-137, 315 |
巻 | 32 |
出版ステータス | Published - 1989 |
外部発表 | はい |
イベント | IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) - New York, NY, USA 継続期間: 1989 2 15 → 1989 2 17 |
Other
Other | IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC 1989) |
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City | New York, NY, USA |
Period | 89/2/15 → 89/2/17 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering