1.2GFLOPS neural network chip exhibiting fast convergence

Yoshikazu Kondo*, Yuichi Koshiba, Yutaka Arima, Mitsuhiro Murasaki, Tuyoshi Yamada, Hiroyuki Amishiro, Hirofumi Shinohara, Hakuro Mori

*この研究の対応する著者

研究成果: Conference contribution

15 被引用数 (Scopus)

抄録

This paper describes a digital neural network chip for use as core in neural network accelerators employs a single-instruction multi-data-stream (SIMD architecture and includes twelve 24b floating-point processing units (PUs), a nonlinear function unit (NFU), and a control unit (CU). Each PU includes 24b×1.28kw local memory and communicates with its neighbor through a shift register ring. This configuration permits both feed-forward and error back propagation (BP) processes to be executed efficiently. The CU, which includes a three stage pipelined sequencer, a 24b×1kw instruction code memory (ICM) and a 144b×256w microcode memory (MCM), broadcasts network parameters (e.g., learning coefficients or temperature parameters) or addresses for local memories through a data and an address bus. Two external memory ports and a ring expansion-port permit large networks to be constructed. The external memory can be expanded by up to 768kW using the two ports.

本文言語English
ホスト出版物のタイトルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
編集者 Anon
出版社Publ by IEEE
ページ218-219
ページ数2
ISBN(印刷版)0780318455
出版ステータスPublished - 1994
外部発表はい
イベントProceedings of the 1994 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
継続期間: 1994 2 161994 2 18

出版物シリーズ

名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Other

OtherProceedings of the 1994 IEEE International Solid-State Circuits Conference
CitySan Francisco, CA, USA
Period94/2/1694/2/18

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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