13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO

Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

研究成果: Conference contribution

32 引用 (Scopus)

抜粋

Scaling power supply voltages (V DD's) of logic circuits down to the sub/near-threshold region is a promising approach to achieve significant power reductions. Circuit delays in the ultra-low voltage region, however, are extremely sensitive to process, voltage, and temperature (PVT) variations, and hence, large timing margins are required for worst-case design. Since such large timing margins reduce the energy efficiency benefits of lower V DD, adaptive V DD control to cope with PVT variations is indispensable for ultra-low voltage circuits. In this paper, an adaptive V DD control system with parity-based error prediction and detection (PEPD) and 0.5-V input fully-integrated digital LDO (DLDO) is proposed.

元の言語English
ホスト出版物のタイトル2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers
ページ486-487
ページ数2
DOI
出版物ステータスPublished - 2012 5 11
イベント59th International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, CA, United States
継続期間: 2012 2 192012 2 23

出版物シリーズ

名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
55
ISSN(印刷物)0193-6530

Other

Other59th International Solid-State Circuits Conference, ISSCC 2012
United States
San Francisco, CA
期間12/2/1912/2/23

    フィンガープリント

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

これを引用

Hirairi, K., Okuma, Y., Fuketa, H., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H., & Sakurai, T. (2012). 13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO. : 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers (pp. 486-487). [6177102] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; 巻数 55). https://doi.org/10.1109/ISSCC.2012.6177102