130-mm2, 256-Mbit NAND flash with shallow trench isolation technology

Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, Koji Sakui

研究成果: Article

18 引用 (Scopus)

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A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 μm is achieved with 0.25-μm STI. The memory cell is shrunk to 0.29 μm2, which realizes a 130-mm2, 256-Mbit flash memory. Peripheral transistors are scaled with memory cells in order to reduce fabrication process steps. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-μs first access time in spite of long and tight pitch bit-line. A 1-kbyte page mode with 35-ns serial data out realizes 25-Mbyte/s read throughput. An incremental step pulse with a bit by bit verify scheme programs 1-k cells in 1-V Vt distribution within 200 μs. That realizes 4.4-Mbyte/s programming throughput.

元の言語English
ページ(範囲)1536-1543
ページ数8
ジャーナルIEEE Journal of Solid-State Circuits
34
発行部数11
DOI
出版物ステータスPublished - 1999 11 1

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

Imamiya, K., Sugiura, Y., Nakamura, H., Himeno, T., Takeuchi, K., Ikehashi, T., Kanda, K., Hosono, K., Shirota, R., Aritome, S., Shimizu, K., Hatakeyama, K., & Sakui, K. (1999). 130-mm2, 256-Mbit NAND flash with shallow trench isolation technology. IEEE Journal of Solid-State Circuits, 34(11), 1536-1543. https://doi.org/10.1109/4.799860