14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique

Kosuke Katayama; Kyoya Takano; Shuhei Amakawa; Takeshi Yoshida; Minoru Fujishima

doi:10.1109/RFIT.2016.7578218

14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique

Kosuke Katayama, Kyoya Takano, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima

研究成果: Conference contribution

9 引用（Scopus）

抜粋

In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.

元の言語	English
ホスト出版物のタイトル	RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology
出版者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子版）	9781509012350
DOI	https://doi.org/10.1109/RFIT.2016.7578218
出版物ステータス	Published - 2016 9 27
外部発表	Yes
イベント	2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016 - Taipei, Taiwan, Province of China 継続期間: 2016 8 24 → 2016 8 26

Other

Other	2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016
国	Taiwan, Province of China
市	Taipei
期間	16/8/24 → 16/8/26

フィンガープリント

ASJC Scopus subject areas

Computer Networks and Communications
Electrical and Electronic Engineering
Instrumentation

これを引用

Katayama, K., Takano, K., Amakawa, S., Yoshida, T., & Fujishima, M. (2016). 14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique. ： RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology [7578218] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RFIT.2016.7578218

14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique. / Katayama, Kosuke; Takano, Kyoya; Amakawa, Shuhei; Yoshida, Takeshi; Fujishima, Minoru.

RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology. Institute of Electrical and Electronics Engineers Inc., 2016. 7578218.

研究成果: Conference contribution

Katayama, K, Takano, K, Amakawa, S, Yoshida, T & Fujishima, M 2016, 14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique. ： RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology., 7578218, Institute of Electrical and Electronics Engineers Inc., 2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016, Taipei, Taiwan, Province of China, 16/8/24. https://doi.org/10.1109/RFIT.2016.7578218

Katayama K, Takano K, Amakawa S, Yoshida T, Fujishima M. 14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique. ： RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology. Institute of Electrical and Electronics Engineers Inc. 2016. 7578218 https://doi.org/10.1109/RFIT.2016.7578218

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BT - RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology

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文献にアクセス

10.1109/RFIT.2016.7578218