14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique

Kosuke Katayama, Kyoya Takano, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima

研究成果: Conference contribution

10 被引用数 (Scopus)

抄録

In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.

本文言語English
ホスト出版物のタイトルRFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781509012350
DOI
出版ステータスPublished - 2016 9 27
外部発表はい
イベント2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016 - Taipei, Taiwan, Province of China
継続期間: 2016 8 242016 8 26

Other

Other2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016
CountryTaiwan, Province of China
CityTaipei
Period16/8/2416/8/26

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering
  • Instrumentation

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