14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique

Kosuke Katayama; Kyoya Takano; Shuhei Amakawa; Takeshi Yoshida; Minoru Fujishima

doi:10.1109/RFIT.2016.7578218

14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique

Kosuke Katayama, Kyoya Takano, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima

研究成果: Conference contribution

10 被引用数 (Scopus)

抄録

In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.

本文言語	English
ホスト出版物のタイトル	RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology
出版社	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子版）	9781509012350
DOI	https://doi.org/10.1109/RFIT.2016.7578218
出版ステータス	Published - 2016 9 27
外部発表	はい
イベント	2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016 - Taipei, Taiwan, Province of China 継続期間: 2016 8 24 → 2016 8 26

Other

Other	2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016
Country	Taiwan, Province of China
City	Taipei
Period	16/8/24 → 16/8/26

ASJC Scopus subject areas

Computer Networks and Communications
Electrical and Electronic Engineering
Instrumentation

文献へのアクセス

10.1109/RFIT.2016.7578218

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引用スタイル

Katayama, K., Takano, K., Amakawa, S., Yoshida, T., & Fujishima, M. (2016). 14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique. In RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology [7578218] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RFIT.2016.7578218

14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique. / Katayama, Kosuke; Takano, Kyoya; Amakawa, Shuhei; Yoshida, Takeshi; Fujishima, Minoru.

RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology. Institute of Electrical and Electronics Engineers Inc., 2016. 7578218.

研究成果: Conference contribution

Katayama, K, Takano, K, Amakawa, S, Yoshida, T & Fujishima, M 2016, 14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique. in RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology., 7578218, Institute of Electrical and Electronics Engineers Inc., 2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016, Taipei, Taiwan, Province of China, 16/8/24. https://doi.org/10.1109/RFIT.2016.7578218

@inproceedings{dafe99493c284e679020cd9b8d39b4c6,

title = "14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique",

abstract = "In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.",

keywords = "Bias optimization, circuit modeling, figure of merit, reduction of measurement",

author = "Kosuke Katayama and Kyoya Takano and Shuhei Amakawa and Takeshi Yoshida and Minoru Fujishima",

year = "2016",

month = sep,

day = "27",

doi = "10.1109/RFIT.2016.7578218",

language = "English",

booktitle = "RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016 ; Conference date: 24-08-2016 Through 26-08-2016",

}

TY - GEN

T1 - 14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique

AU - Katayama, Kosuke

AU - Takano, Kyoya

AU - Amakawa, Shuhei

AU - Yoshida, Takeshi

AU - Fujishima, Minoru

PY - 2016/9/27

Y1 - 2016/9/27

N2 - In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.

AB - In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.

KW - Bias optimization

KW - circuit modeling

KW - figure of merit

KW - reduction of measurement

UR - http://www.scopus.com/inward/record.url?scp=84994766548&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84994766548&partnerID=8YFLogxK

U2 - 10.1109/RFIT.2016.7578218

DO - 10.1109/RFIT.2016.7578218

M3 - Conference contribution

AN - SCOPUS:84994766548

BT - RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016

Y2 - 24 August 2016 through 26 August 2016

ER -