TY - GEN
T1 - 14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique
AU - Katayama, Kosuke
AU - Takano, Kyoya
AU - Amakawa, Shuhei
AU - Yoshida, Takeshi
AU - Fujishima, Minoru
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/9/27
Y1 - 2016/9/27
N2 - In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.
AB - In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.
KW - Bias optimization
KW - circuit modeling
KW - figure of merit
KW - reduction of measurement
UR - http://www.scopus.com/inward/record.url?scp=84994766548&partnerID=8YFLogxK
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U2 - 10.1109/RFIT.2016.7578218
DO - 10.1109/RFIT.2016.7578218
M3 - Conference contribution
AN - SCOPUS:84994766548
T3 - RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology
BT - RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016
Y2 - 24 August 2016 through 26 August 2016
ER -