14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique

Kosuke Katayama, Kyoya Takano, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima

研究成果: Conference contribution

9 引用 (Scopus)

抜粋

In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.

元の言語English
ホスト出版物のタイトルRFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology
出版者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9781509012350
DOI
出版物ステータスPublished - 2016 9 27
外部発表Yes
イベント2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016 - Taipei, Taiwan, Province of China
継続期間: 2016 8 242016 8 26

Other

Other2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016
Taiwan, Province of China
Taipei
期間16/8/2416/8/26

    フィンガープリント

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering
  • Instrumentation

これを引用

Katayama, K., Takano, K., Amakawa, S., Yoshida, T., & Fujishima, M. (2016). 14.4-dB CMOS D-band low-noise amplifier with 22.6-mW power consumption utilizing bias-optimization technique. : RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology [7578218] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RFIT.2016.7578218