抄録
In this paper, we propose a method of reducing the number of measurements when a bias optimization of an amplifier is required. We also provide a method of reconstructing an entire model of the amplifier from the reduced number of measurement results. We fabricated an eight-stage D-band low-noise amplifier (LNA) using a 65-nm CMOS technology. Applying these methods to this LNA to maximize a figure of merit, we obtained a 14.4-dB gain with ultra-low power consumption of 22.6 mW.
本文言語 | English |
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ホスト出版物のタイトル | RFIT 2016 - 2016 IEEE International Symposium on Radio-Frequency Integration Technology |
出版社 | Institute of Electrical and Electronics Engineers Inc. |
ISBN(電子版) | 9781509012350 |
DOI | |
出版ステータス | Published - 2016 9 27 |
外部発表 | はい |
イベント | 2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016 - Taipei, Taiwan, Province of China 継続期間: 2016 8 24 → 2016 8 26 |
Other
Other | 2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016 |
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Country | Taiwan, Province of China |
City | Taipei |
Period | 16/8/24 → 16/8/26 |
ASJC Scopus subject areas
- Computer Networks and Communications
- Electrical and Electronic Engineering
- Instrumentation