16Mb DRAM/SOI technologies for sub-1V operation

T. Oashi, T. Eimori, F. Morishita, T. Iwamatsu, Y. Yamaguchi, F. Okuda, K. Shimomura, H. Shimano, N. Sakashita, K. Arimoto, Y. Inoue, S. Komori, M. Inuishi, T. Nishimura, H. Miyoshi

研究成果: Conference article

6 引用 (Scopus)

抜粋

Extra low voltage DRAM/SOI technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFET's, and (4) reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16MDRAM/SOI was successfully realized and functional operation was obtained at very low supply voltage below 1V.

元の言語English
ページ(範囲)609-612
ページ数4
ジャーナルTechnical Digest - International Electron Devices Meeting
出版物ステータスPublished - 1996 12 1
外部発表Yes
イベントProceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA
継続期間: 1996 12 81996 12 11

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

フィンガープリント 16Mb DRAM/SOI technologies for sub-1V operation' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

  • これを引用

    Oashi, T., Eimori, T., Morishita, F., Iwamatsu, T., Yamaguchi, Y., Okuda, F., Shimomura, K., Shimano, H., Sakashita, N., Arimoto, K., Inoue, Y., Komori, S., Inuishi, M., Nishimura, T., & Miyoshi, H. (1996). 16Mb DRAM/SOI technologies for sub-1V operation. Technical Digest - International Electron Devices Meeting, 609-612.