18-BIT FLOATING-POINT SIGNAL PROCESSOR VLSI WITH AN ON-CHIP 512W DUAL-PORT RAM.

Hironori Yamauchi*, Takao Kaneko, Tsutomu Kobayashi, Atsushi Iwata, Sadayasu Ono

*この研究の対応する著者

研究成果: Conference article査読

1 被引用数 (Scopus)

抄録

A brand-new floating-point digital speech signal processor (DSSP) VLSI, intended for a wide range of applications in speech processing, has been developed. For speech applications, a wide-dynamic-range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. It is shown at length how the floating-point data format and hardware architecture meet this requirement. The DSSP, which is fabricated using 2. 5 mu m CMOS technology, completes almost all the floating-point operations within a 150-ns machine-cycle.

本文言語English
ページ(範囲)204-207
ページ数4
ジャーナルICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
出版ステータスPublished - 1985 12 1
外部発表はい

ASJC Scopus subject areas

  • ソフトウェア
  • 信号処理
  • 電子工学および電気工学

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