1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times

T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Tokutome, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

研究成果: Conference contribution

50 被引用数 (Scopus)

抄録

A 1Mb nonvolatile STT-RAM using the 4T-2MTJ cell is designed and fabricated using 90nm CMOS and MTJ processes. 32 cells along a word line (WL) are simultaneously power-gated with quick wake-up/power-off times of 1.0ns/200ps, respectively, to reduce operation power and to eliminate standby power of the chip. The cell is experimentally shown to retain data with static noise margin (SNM) 0.32V under V dd=1V. The 1Mb chip with 2.19μm 2 cell is successfully operated with array access time of 8ns and read power of 10.7mW under 10ns cycle. The macro size of 1Mb STT-RAM is predicted to become smaller than the 1Mb 6T-SRAM in 45nm and beyond.

本文言語English
ホスト出版物のタイトル2012 Symposium on VLSI Circuits, VLSIC 2012
ページ46-47
ページ数2
DOI
出版ステータスPublished - 2012 9 28
外部発表はい
イベント2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States
継続期間: 2012 6 132012 6 15

出版物シリーズ

名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2012 Symposium on VLSI Circuits, VLSIC 2012
CountryUnited States
CityHonolulu, HI
Period12/6/1312/6/15

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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