2.37-dBm-output 288-310 GHz frequency multiplier in 40 nm CMOS

Kosuke Katayama, Kyoya Takano, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima

研究成果: Conference contribution

4 引用 (Scopus)

抜粋

We introduce a 288-310 GHz frequency multiplier fabricated with 40 nm CMOS technology. With 410.3 mW power consumption, this frequency multiplier has a conversion gain of 4.52 dB including that of its driver amplifier. The proposed system for input power/phase control of the power combiner enhances the output power of the frequency multiplier to 2.37 dBm at 300 GHz.

元の言語English
ホスト出版物のタイトル2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017
出版者Institute of Electrical and Electronics Engineers Inc.
ページ28-30
ページ数3
ISBN(電子版)9781509040360
DOI
出版物ステータスPublished - 2017 9 20
外部発表Yes
イベント2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017 - Seoul, Korea, Republic of
継続期間: 2017 8 302017 9 1

Other

Other2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017
Korea, Republic of
Seoul
期間17/8/3017/9/1

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering
  • Instrumentation

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  • これを引用

    Katayama, K., Takano, K., Amakawa, S., Yoshida, T., & Fujishima, M. (2017). 2.37-dBm-output 288-310 GHz frequency multiplier in 40 nm CMOS. : 2017 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2017 (pp. 28-30). [8048279] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RFIT.2017.8048279