A post-fabrication dual supply voltage (V DD) control (PDVC) of multiple voltage domains is proposed for a minimum operating voltage (V DDmin)-limited ultra low voltage logic circuits. PDVC effectively reduces an average V DD below V DDmin, thereby reducing the power consumption of logic circuits. PDVC is applied to a DES CODEC'S circuit fabricated in 65nm CMOS. The layout of DES CODEC'S is divided into 64 V DD domains and each domain size is 54μm x 63.2μm. High V DD (V DDH) or low V DD (V DDL) is applied to each domain and the selection of V DD's is performed based on multiple built-in self tests. V DDH is selected in V DDmin-critical domains, while V DDL is selected in V DDmin-non-critical domains. A maximum 24% power reduction was measured with the proposed PDVC at 300kHz, V DDH =437mV, and V DDL =397mV.