24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V DDmin limited ultra low voltage logic circuits

Tadashi Yasufuku*, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai

*この研究の対応する著者

研究成果: Conference contribution

9 被引用数 (Scopus)

抄録

A post-fabrication dual supply voltage (V DD) control (PDVC) of multiple voltage domains is proposed for a minimum operating voltage (V DDmin)-limited ultra low voltage logic circuits. PDVC effectively reduces an average V DD below V DDmin, thereby reducing the power consumption of logic circuits. PDVC is applied to a DES CODEC'S circuit fabricated in 65nm CMOS. The layout of DES CODEC'S is divided into 64 V DD domains and each domain size is 54μm x 63.2μm. High V DD (V DDH) or low V DD (V DDL) is applied to each domain and the selection of V DD's is performed based on multiple built-in self tests. V DDH is selected in V DDmin-critical domains, while V DDL is selected in V DDmin-non-critical domains. A maximum 24% power reduction was measured with the proposed PDVC at 300kHz, V DDH =437mV, and V DDL =397mV.

本文言語English
ホスト出版物のタイトルProceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012
ページ586-591
ページ数6
DOI
出版ステータスPublished - 2012 7 16
外部発表はい
イベント13th International Symposium on Quality Electronic Design, ISQED 2012 - Santa Clara, CA, United States
継続期間: 2012 3 192012 3 21

出版物シリーズ

名前Proceedings - International Symposium on Quality Electronic Design, ISQED
ISSN(印刷版)1948-3287
ISSN(電子版)1948-3295

Other

Other13th International Symposium on Quality Electronic Design, ISQED 2012
国/地域United States
CitySanta Clara, CA
Period12/3/1912/3/21

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学
  • 安全性、リスク、信頼性、品質管理

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