25-ns 256K ×1/64K × 4 CMOS SRAM's

Shinpei Kayano; Katsuki Ichinose; Yoshio Kohno; Hirofumi Shinohara; Kenji Anami; Shuji Murakami; Tomohisa Wada; Yuji Kawai; Yoichi Akasaka

doi:10.1109/JSSC.1986.1052596

25-ns 256K ×1/64K × 4 CMOS SRAM's

Shinpei Kayano, Katsuki Ichinose, Yoshio Kohno, Hirofumi Shinohara, Kenji Anami, Shuji Murakami, Tomohisa Wada, Yuji Kawai, Yoichi Akasaka

研究成果: Article › 査読

10 被引用数 (Scopus)

抄録

This paper describes 25-ns 256K CMOS static RAM's (SRAM‘s). Through a metal option, either 256K word × 1-bit or 64K word×4-bit organization is obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address transition detector (ATD) circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-µm double-polysilicon and single-metal process technology with polycide gate offers a memory cell size of 90 µm2 and a chip size of 47.4 mm2.

本文言語	English
ページ（範囲）	686-691
ページ数	6
ジャーナル	IEEE Journal of Solid-State Circuits
巻	21
号	5
DOI	https://doi.org/10.1109/JSSC.1986.1052596
出版ステータス	Published - 1986 10月
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

文献へのアクセス

10.1109/JSSC.1986.1052596

他のファイルとリンク

引用スタイル

@article{e05ddb30ad1b4fc7be3f8406ebd0a65a,

title = "25-ns 256K ×1/64K × 4 CMOS SRAM's",

abstract = "This paper describes 25-ns 256K CMOS static RAM's (SRAM{\textquoteleft}s). Through a metal option, either 256K word × 1-bit or 64K word×4-bit organization is obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address transition detector (ATD) circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-µm double-polysilicon and single-metal process technology with polycide gate offers a memory cell size of 90 µm2 and a chip size of 47.4 mm2.",

author = "Shinpei Kayano and Katsuki Ichinose and Yoshio Kohno and Hirofumi Shinohara and Kenji Anami and Shuji Murakami and Tomohisa Wada and Yuji Kawai and Yoichi Akasaka",

year = "1986",

month = oct,

doi = "10.1109/JSSC.1986.1052596",

language = "English",

volume = "21",

pages = "686--691",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - 25-ns 256K ×1/64K × 4 CMOS SRAM's

AU - Kayano, Shinpei

AU - Ichinose, Katsuki

AU - Kohno, Yoshio

AU - Shinohara, Hirofumi

AU - Anami, Kenji

AU - Murakami, Shuji

AU - Wada, Tomohisa

AU - Kawai, Yuji

AU - Akasaka, Yoichi

PY - 1986/10

Y1 - 1986/10

N2 - This paper describes 25-ns 256K CMOS static RAM's (SRAM‘s). Through a metal option, either 256K word × 1-bit or 64K word×4-bit organization is obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address transition detector (ATD) circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-µm double-polysilicon and single-metal process technology with polycide gate offers a memory cell size of 90 µm2 and a chip size of 47.4 mm2.

AB - This paper describes 25-ns 256K CMOS static RAM's (SRAM‘s). Through a metal option, either 256K word × 1-bit or 64K word×4-bit organization is obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address transition detector (ATD) circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-µm double-polysilicon and single-metal process technology with polycide gate offers a memory cell size of 90 µm2 and a chip size of 47.4 mm2.

UR - http://www.scopus.com/inward/record.url?scp=77956241702&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77956241702&partnerID=8YFLogxK

U2 - 10.1109/JSSC.1986.1052596

DO - 10.1109/JSSC.1986.1052596

M3 - Article

AN - SCOPUS:77956241702

VL - 21

SP - 686

EP - 691

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 5

ER -

25-ns 256K ×1/64K × 4 CMOS SRAM's

抄録

ASJC Scopus subject areas

文献へのアクセス

他のファイルとリンク

フィンガープリント

引用スタイル