This paper describes 25-ns 256K CMOS static RAM's (SRAM‘s). Through a metal option, either 256K word × 1-bit or 64K word×4-bit organization is obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address transition detector (ATD) circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-µm double-polysilicon and single-metal process technology with polycide gate offers a memory cell size of 90 µm2 and a chip size of 47.4 mm2.
ASJC Scopus subject areas