25-ns 256K ×1/64K × 4 CMOS SRAM's

Shinpei Kayano; Katsuki Ichinose; Yoshio Kohno; Hirofumi Shinohara; Kenji Anami; Shuji Murakami; Tomohisa Wada; Yuji Kawai; Yoichi Akasaka

doi:10.1109/JSSC.1986.1052596

25-ns 256K ×1/64K × 4 CMOS SRAM's

Shinpei Kayano, Katsuki Ichinose, Yoshio Kohno, Hirofumi Shinohara, Kenji Anami, Shuji Murakami, Tomohisa Wada, Yuji Kawai, Yoichi Akasaka

研究成果: Article › 査読

10 被引用数 (Scopus)

抄録

This paper describes 25-ns 256K CMOS static RAM's (SRAM‘s). Through a metal option, either 256K word × 1-bit or 64K word×4-bit organization is obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address transition detector (ATD) circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-µm double-polysilicon and single-metal process technology with polycide gate offers a memory cell size of 90 µm2 and a chip size of 47.4 mm2.

本文言語	English
ページ（範囲）	686-691
ページ数	6
ジャーナル	IEEE Journal of Solid-State Circuits
巻	21
号	5
DOI	https://doi.org/10.1109/JSSC.1986.1052596
出版ステータス	Published - 1986 10
外部発表	はい

ASJC Scopus subject areas

Electrical and Electronic Engineering

文献へのアクセス

10.1109/JSSC.1986.1052596

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引用スタイル

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AU - Kayano, Shinpei

AU - Ichinose, Katsuki

AU - Kohno, Yoshio

AU - Shinohara, Hirofumi

AU - Anami, Kenji

AU - Murakami, Shuji

AU - Wada, Tomohisa

AU - Kawai, Yuji

AU - Akasaka, Yoichi

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