抄録
A 3.3 V-only 16 Mb DINOR flash memory is described. The flash memory has 47 ns random access time and 1 MB programmable throughput. Power consumption in program operation is 60 m W. The memory is fabricated using a 0.5 micrometer design rule, double-layer aluminum, triple-layer polysilicon, triple-well CMOS. The effective memory cell is 1.4×1.35 μm 2. 256 B page buffer, optimized source/drain memory cell structure and efficient charge pump result in high speed, low power consumption, and low cost.
本文言語 | English |
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ホスト出版物のタイトル | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
出版社 | IEEE |
巻 | 38 |
出版ステータス | Published - 1995 2月 |
外部発表 | はい |
イベント | Proceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA 継続期間: 1995 2月 15 → 1995 2月 17 |
Other
Other | Proceedings of the 1995 IEEE International Solid-State Circuits Conference |
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City | San Francisco, CA, USA |
Period | 95/2/15 → 95/2/17 |
ASJC Scopus subject areas
- ハードウェアとアーキテクチャ
- 電子工学および電気工学