3.3 V-only 16 Mb DINOR flash memory

Shin ichi Kobayashi; Masaaki Mihara; Yoshikazu Miyawaki; Motoharu Ishii; Tomoshi Futatsuya; Akira Hosogane; Atsushi Ohba; Yasushi Terada; Natsuo Ajika; Yuichi Kunori; Kojiro Yuzuriha; Masahiro Hatanaka; Hirokazu Miyoshi; Tsutomu Yoshihara; Yuji Uji

3.3 V-only 16 Mb DINOR flash memory

Shin ichi Kobayashi, Masaaki Mihara, Yoshikazu Miyawaki, Motoharu Ishii, Tomoshi Futatsuya, Akira Hosogane, Atsushi Ohba, Yasushi Terada, Natsuo Ajika, Yuichi Kunori, Kojiro Yuzuriha, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara, Yuji Uji

研究成果: Conference contribution

25 被引用数 (Scopus)

抄録

A 3.3 V-only 16 Mb DINOR flash memory is described. The flash memory has 47 ns random access time and 1 MB programmable throughput. Power consumption in program operation is 60 m W. The memory is fabricated using a 0.5 micrometer design rule, double-layer aluminum, triple-layer polysilicon, triple-well CMOS. The effective memory cell is 1.4×1.35 μm ². 256 B page buffer, optimized source/drain memory cell structure and efficient charge pump result in high speed, low power consumption, and low cost.

本文言語	English
ホスト出版物のタイトル	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
出版社	IEEE
巻	38
出版ステータス	Published - 1995 2
外部発表	はい
イベント	Proceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA 継続期間: 1995 2 15 → 1995 2 17

Other

Other	Proceedings of the 1995 IEEE International Solid-State Circuits Conference
City	San Francisco, CA, USA
Period	95/2/15 → 95/2/17

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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引用スタイル

3.3 V-only 16 Mb DINOR flash memory. / Kobayashi, Shin ichi; Mihara, Masaaki; Miyawaki, Yoshikazu; Ishii, Motoharu; Futatsuya, Tomoshi; Hosogane, Akira; Ohba, Atsushi; Terada, Yasushi; Ajika, Natsuo; Kunori, Yuichi; Yuzuriha, Kojiro; Hatanaka, Masahiro; Miyoshi, Hirokazu; Yoshihara, Tsutomu; Uji, Yuji.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 38 IEEE, 1995.

研究成果: Conference contribution

Kobayashi, SI, Mihara, M, Miyawaki, Y, Ishii, M, Futatsuya, T, Hosogane, A, Ohba, A, Terada, Y, Ajika, N, Kunori, Y, Yuzuriha, K, Hatanaka, M, Miyoshi, H, Yoshihara, T & Uji, Y 1995, 3.3 V-only 16 Mb DINOR flash memory. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 38, IEEE, Proceedings of the 1995 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 95/2/15.

Kobayashi, Shin ichi ; Mihara, Masaaki ; Miyawaki, Yoshikazu ; Ishii, Motoharu ; Futatsuya, Tomoshi ; Hosogane, Akira ; Ohba, Atsushi ; Terada, Yasushi ; Ajika, Natsuo ; Kunori, Yuichi ; Yuzuriha, Kojiro ; Hatanaka, Masahiro ; Miyoshi, Hirokazu ; Yoshihara, Tsutomu ; Uji, Yuji. / 3.3 V-only 16 Mb DINOR flash memory. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 38 IEEE, 1995.

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abstract = "A 3.3 V-only 16 Mb DINOR flash memory is described. The flash memory has 47 ns random access time and 1 MB programmable throughput. Power consumption in program operation is 60 m W. The memory is fabricated using a 0.5 micrometer design rule, double-layer aluminum, triple-layer polysilicon, triple-well CMOS. The effective memory cell is 1.4×1.35 μm 2. 256 B page buffer, optimized source/drain memory cell structure and efficient charge pump result in high speed, low power consumption, and low cost. ",

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AU - Kobayashi, Shin ichi

AU - Mihara, Masaaki

AU - Miyawaki, Yoshikazu

AU - Ishii, Motoharu

AU - Futatsuya, Tomoshi

AU - Hosogane, Akira

AU - Ohba, Atsushi

AU - Terada, Yasushi

AU - Ajika, Natsuo

AU - Kunori, Yuichi

AU - Yuzuriha, Kojiro

AU - Hatanaka, Masahiro

AU - Miyoshi, Hirokazu

AU - Yoshihara, Tsutomu

AU - Uji, Yuji

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AB - A 3.3 V-only 16 Mb DINOR flash memory is described. The flash memory has 47 ns random access time and 1 MB programmable throughput. Power consumption in program operation is 60 m W. The memory is fabricated using a 0.5 micrometer design rule, double-layer aluminum, triple-layer polysilicon, triple-well CMOS. The effective memory cell is 1.4×1.35 μm 2. 256 B page buffer, optimized source/drain memory cell structure and efficient charge pump result in high speed, low power consumption, and low cost.

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