34ns 256Mb DRAM with boosted sense-ground scheme

Mikio Asakura, Tsukasa Ohishi, Masaki Tsukude, Shigeki Tomishima, Hideto Hidaka, Kazutami Anmoto, Kazuyasu Fujishima, Takahisa Eimori, Yoshikazu Ohno, Tadashi Nishimura, Masatoshi Yasunaga, Takashi Kondon, Shin ichi Satoh, Tsutomu Yoshihara, Kiyoshi Demizu

研究成果: Conference contribution

16 被引用数 (Scopus)

抄録

This paper describes boosted sense-ground (BSG) scheme extends the data retention time of a 256Mb DRAM. This scheme features a `L' bitline level slightly boosted to suppress sub-threshold current of unselected memory-cell access transistors in the activated memory mats for the sake of the effective negative gate-source voltage (Vgs). A chip-scale package (CSP) technique is used to reduce package size to near chip size. A perspective view of the package is shown. The experimental 256Mb DRAM uses 0.25μm CMOS technology with triple-level metal. cs is 25fF with a 0. 72μm2 cell. The chip is 304mm2. The power supply is regulated internally to 2.5V.

本文言語English
ホスト出版物のタイトルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
編集者 Anon
Place of PublicationPiscataway, NJ, United States
出版社Publ by IEEE
ページ140-141
ページ数2
ISBN(印刷版)0780318455
出版ステータスPublished - 1994
外部発表はい
イベントProceedings of the 1994 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
継続期間: 1994 2 161994 2 18

Other

OtherProceedings of the 1994 IEEE International Solid-State Circuits Conference
CitySan Francisco, CA, USA
Period94/2/1694/2/18

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学
  • 工学(全般)

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