34ns 256Mb DRAM with boosted sense-ground scheme

Mikio Asakura, Tsukasa Ohishi, Masaki Tsukude, Shigeki Tomishima, Hideto Hidaka, Kazutami Anmoto, Kazuyasu Fujishima, Takahisa Eimori, Yoshikazu Ohno, Tadashi Nishimura, Masatoshi Yasunaga, Takashi Kondon, Shin ichi Satoh, Tsutomu Yoshihara, Kiyoshi Demizu

研究成果: Conference contribution

16 引用 (Scopus)

抄録

This paper describes boosted sense-ground (BSG) scheme extends the data retention time of a 256Mb DRAM. This scheme features a `L' bitline level slightly boosted to suppress sub-threshold current of unselected memory-cell access transistors in the activated memory mats for the sake of the effective negative gate-source voltage (Vgs). A chip-scale package (CSP) technique is used to reduce package size to near chip size. A perspective view of the package is shown. The experimental 256Mb DRAM uses 0.25μm CMOS technology with triple-level metal. cs is 25fF with a 0. 72μm2 cell. The chip is 304mm2. The power supply is regulated internally to 2.5V.

元の言語English
ホスト出版物のタイトルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
編集者 Anon
出版場所Piscataway, NJ, United States
出版者Publ by IEEE
ページ140-141
ページ数2
ISBN(印刷物)0780318455
出版物ステータスPublished - 1994
外部発表Yes
イベントProceedings of the 1994 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
継続期間: 1994 2 161994 2 18

Other

OtherProceedings of the 1994 IEEE International Solid-State Circuits Conference
San Francisco, CA, USA
期間94/2/1694/2/18

Fingerprint

Dynamic random access storage
Chip scale packages
Data storage equipment
Transistors
Electric potential
Metals

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Engineering(all)

これを引用

Asakura, M., Ohishi, T., Tsukude, M., Tomishima, S., Hidaka, H., Anmoto, K., ... Demizu, K. (1994). 34ns 256Mb DRAM with boosted sense-ground scheme. : Anon (版), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (pp. 140-141). Piscataway, NJ, United States: Publ by IEEE.

34ns 256Mb DRAM with boosted sense-ground scheme. / Asakura, Mikio; Ohishi, Tsukasa; Tsukude, Masaki; Tomishima, Shigeki; Hidaka, Hideto; Anmoto, Kazutami; Fujishima, Kazuyasu; Eimori, Takahisa; Ohno, Yoshikazu; Nishimura, Tadashi; Yasunaga, Masatoshi; Kondon, Takashi; Satoh, Shin ichi; Yoshihara, Tsutomu; Demizu, Kiyoshi.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 版 / Anon. Piscataway, NJ, United States : Publ by IEEE, 1994. p. 140-141.

研究成果: Conference contribution

Asakura, M, Ohishi, T, Tsukude, M, Tomishima, S, Hidaka, H, Anmoto, K, Fujishima, K, Eimori, T, Ohno, Y, Nishimura, T, Yasunaga, M, Kondon, T, Satoh, SI, Yoshihara, T & Demizu, K 1994, 34ns 256Mb DRAM with boosted sense-ground scheme. : Anon (版), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Publ by IEEE, Piscataway, NJ, United States, pp. 140-141, Proceedings of the 1994 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 94/2/16.
Asakura M, Ohishi T, Tsukude M, Tomishima S, Hidaka H, Anmoto K その他. 34ns 256Mb DRAM with boosted sense-ground scheme. : Anon, 編集者, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Piscataway, NJ, United States: Publ by IEEE. 1994. p. 140-141
Asakura, Mikio ; Ohishi, Tsukasa ; Tsukude, Masaki ; Tomishima, Shigeki ; Hidaka, Hideto ; Anmoto, Kazutami ; Fujishima, Kazuyasu ; Eimori, Takahisa ; Ohno, Yoshikazu ; Nishimura, Tadashi ; Yasunaga, Masatoshi ; Kondon, Takashi ; Satoh, Shin ichi ; Yoshihara, Tsutomu ; Demizu, Kiyoshi. / 34ns 256Mb DRAM with boosted sense-ground scheme. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 編集者 / Anon. Piscataway, NJ, United States : Publ by IEEE, 1994. pp. 140-141
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