抄録
In 3D integrated circuit (3D-IC), there are two or more layers of active electronic components which are integrated both vertically and horizontally. Through-silicon-via (TSV) is used as the vertical electrical connection which enables a great deal of functionality packed into a small footprint. In this work we solve the signal TSV assignment problem in 3D-IC taking thermal problem into consideration, while only wire length is concerned in the previous work. Firstly, we propose a multilevel node-weight-oriented flow assignment algorithm to reduce wire length and temperature simultaneously. During the evaluation of wire length and temperature result, we use a thermal estimation model to evaluate temperature, where compression storage method with LU decomposition is adopted to improve algorithm efficiency. Moreover, we implement the remove and reassign optimization method which helps further optimize the TSV assignment results. The experimental results show that our algorithm provides better solution with wire length reduction and temperature decrease.
本文言語 | English |
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ホスト出版物のタイトル | 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017 |
出版社 | Institute of Electrical and Electronics Engineers Inc. |
ページ | 1-8 |
ページ数 | 8 |
巻 | 2017-January |
ISBN(電子版) | 9781509064625 |
DOI | |
出版ステータス | Published - 2017 11月 13 |
イベント | 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017 - Thessaloniki, Greece 継続期間: 2017 9月 25 → 2017 9月 27 |
Other
Other | 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017 |
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国/地域 | Greece |
City | Thessaloniki |
Period | 17/9/25 → 17/9/27 |
ASJC Scopus subject areas
- モデリングとシミュレーション
- コンピュータ ネットワークおよび通信
- ハードウェアとアーキテクチャ
- エネルギー工学および電力技術
- 電子工学および電気工学
- 制御と最適化