4. 5NS 256K CMOS SRAM WITH TRI-LEVEL WORD LINE.

Hirofumi Shinohara, Kenji Anami, Katsuki Ichinose, Tomehisa Wada, Yoshio Kohno, Yuji Kawai, Yoichi Akasaka, Shinpei Kayano

研究成果: Conference article査読

7 被引用数 (Scopus)

抄録

Summary form only given. The 32K multiplied by 8-b static RAM includes an address-transition-activated circuit combined with a tri-level word line, which affords an active power of 7 mW at 1 MHz and a peak current of 40 mA. An address access time of 45 ns has been obtained. The RAM was fabricated with double-polysilicon single-aluminum CMOS technology. The gate lengths of the MOS transistors are scaled to 1. 3 mu (N channel) and 1. 8 mu (P channel) for fast access time. The use of 1. 3- mu m design rules permits layout of a NMOS memory cell with high resistance loads in area 8. 0 mu multiplied by 14. 5 mu area.

本文言語English
ページ(範囲)62-63
ページ数2
ジャーナルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
出版ステータスPublished - 1985
外部発表はい

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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