抄録
A 5-V 4-Mb word multiplied by 1-b/1-Mb word multiplied by 4-b dynamic RAM with a static column mode and fast page mode has been built in a 0. 8 mu m twin-tub CMOS technology with single-metal, two-polycide, and single poly-Si interconnections. It uses an innovative folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell that measures 10. 9 mu m**2 and requires only a 2 mu m trench to obtain a storage capacitor of 50 fF with 10 nm SiO//2 equivalent dielectric film. A shared-PMOS sense-amplifier architecture used in this DRAM provides a low power consumption, small C//B-to-C//S capacitance ratio, and accurate reference level for the nonboosted word-line scheme with little area penalty. These concepts have allowed the DRAM to be housed in the industry standard 300 mil dual-in-line package with performances of 90 ns RAS access time and 30 ns column address access time.
本文言語 | English |
---|---|
ページ(範囲) | 643-650 |
ページ数 | 8 |
ジャーナル | IEEE Journal of Solid-State Circuits |
巻 | SC-22 |
号 | 5 |
出版ステータス | Published - 1987 10月 |
外部発表 | はい |
ASJC Scopus subject areas
- 電子工学および電気工学