抄録
A 5-V 4-Mb word multiplied by 1-b/1-Mb word multiplied by 4-b dynamic RAM with a static column mode and fast page mode has been built in a 0. 8 mu m twin-tub CMOS technology with single-metal, two-polycide, and single poly-Si interconnections. It uses an innovative folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell that measures 10. 9 mu m**2 and requires only a 2 mu m trench to obtain a storage capacitor of 50 fF with 10 nm SiO//2 equivalent dielectric film. A shared-PMOS sense-amplifier architecture used in this DRAM provides a low power consumption, small C//B-to-C//S capacitance ratio, and accurate reference level for the nonboosted word-line scheme with little area penalty. These concepts have allowed the DRAM to be housed in the industry standard 300 mil dual-in-line package with performances of 90 ns RAS access time and 30 ns column address access time.
| 元の言語 | English |
|---|---|
| ページ（範囲） | 643-650 |
| ページ数 | 8 |
| ジャーナル | IEEE Journal of Solid-State Circuits |
| 巻 | SC-22 |
| 発行部数 | 5 |
| 出版物ステータス | Published - 1987 10 |
| 外部発表 | Yes |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
これを引用
4-MBIT DRAM WITH FOLDED-BIT-LINE ADAPTIVE SIDEWALL-ISOLATED CAPACITOR (FASIC) CELL. / Mashiko, Koichiro; Nagatomo, Masao; Arimoto, Kazutami; Matsuda, Yoshio; Furutani, Kiyohiro; Matsukawa, Takayuki; Yamada, Michihiro; Yoshihara, Tsutomu; Nakano, Takao.
：: IEEE Journal of Solid-State Circuits, 巻 SC-22, 番号 5, 10.1987, p. 643-650.研究成果: Article
}
TY - JOUR
T1 - 4-MBIT DRAM WITH FOLDED-BIT-LINE ADAPTIVE SIDEWALL-ISOLATED CAPACITOR (FASIC) CELL.
AU - Mashiko, Koichiro
AU - Nagatomo, Masao
AU - Arimoto, Kazutami
AU - Matsuda, Yoshio
AU - Furutani, Kiyohiro
AU - Matsukawa, Takayuki
AU - Yamada, Michihiro
AU - Yoshihara, Tsutomu
AU - Nakano, Takao
PY - 1987/10
Y1 - 1987/10
N2 - A 5-V 4-Mb word multiplied by 1-b/1-Mb word multiplied by 4-b dynamic RAM with a static column mode and fast page mode has been built in a 0. 8 mu m twin-tub CMOS technology with single-metal, two-polycide, and single poly-Si interconnections. It uses an innovative folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell that measures 10. 9 mu m**2 and requires only a 2 mu m trench to obtain a storage capacitor of 50 fF with 10 nm SiO//2 equivalent dielectric film. A shared-PMOS sense-amplifier architecture used in this DRAM provides a low power consumption, small C//B-to-C//S capacitance ratio, and accurate reference level for the nonboosted word-line scheme with little area penalty. These concepts have allowed the DRAM to be housed in the industry standard 300 mil dual-in-line package with performances of 90 ns RAS access time and 30 ns column address access time.
AB - A 5-V 4-Mb word multiplied by 1-b/1-Mb word multiplied by 4-b dynamic RAM with a static column mode and fast page mode has been built in a 0. 8 mu m twin-tub CMOS technology with single-metal, two-polycide, and single poly-Si interconnections. It uses an innovative folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell that measures 10. 9 mu m**2 and requires only a 2 mu m trench to obtain a storage capacitor of 50 fF with 10 nm SiO//2 equivalent dielectric film. A shared-PMOS sense-amplifier architecture used in this DRAM provides a low power consumption, small C//B-to-C//S capacitance ratio, and accurate reference level for the nonboosted word-line scheme with little area penalty. These concepts have allowed the DRAM to be housed in the industry standard 300 mil dual-in-line package with performances of 90 ns RAS access time and 30 ns column address access time.
UR - http://www.scopus.com/inward/record.url?scp=0023436113&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0023436113&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0023436113
VL - SC-22
SP - 643
EP - 650
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 5
ER -