45-NS 256K CMOS STATIC RAM WITH A TRI-LEVEL WORD LINE.

Hirofumi Shinohara, Kenji Anami, Katsuki Ichinose, Tomohisa Wada, Yoshio Kohno, Yuji Kawai, Yoichi Akasaka, Shinpei Kayano

研究成果: Article

4 引用 (Scopus)

抜粋

A 32K words by 8-bit static RAM fabricated with a CMOS technology. is described. The key feature of the RAM is a tri-level word-line, in which an automatic power down by a pulsed word-line in the READ cycle and a power saving by a middle-level word-line in the WRITE cycle are combined. This circuit technique minimizes bitline swing, shortens the precharging time, and depresses the transient current. An improved address transition detection circuit reduces the chip select access time. The sense amplifier uses internally synchronized signals for improved operation. The RAM has a typical access time of 45 ns with an active power dissipation of 7 mW. The peak transient current is less than 40 mA. A double-level polysilicon technology with a 1. 3- mu m design rule allowed layout of the NMOS memory cell in an area of 116. 0 mu m**2 and the die in 49. 6 mm**2.

元の言語English
ジャーナルIEEE Journal of Solid-State Circuits
SC-20
発行部数5
出版物ステータスPublished - 1985 10 1

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

Shinohara, H., Anami, K., Ichinose, K., Wada, T., Kohno, Y., Kawai, Y., Akasaka, Y., & Kayano, S. (1985). 45-NS 256K CMOS STATIC RAM WITH A TRI-LEVEL WORD LINE. IEEE Journal of Solid-State Circuits, SC-20(5).