5. 4 mu M**2 STACKED CAPACITOR DRAM CELL WITH 0. 6 mu M QUADRUPLE-POLYSILICON GATE TECHNOLOGY.

S. Kimura*, Y. Kawamoto, N. Hasegawa, A. Hiraiwa, M. Horiguchi, M. Aoki, T. Kisu, H. Sunami

*この研究の対応する著者

研究成果: Conference contribution

8 被引用数 (Scopus)

抄録

A 5. 4 mu m**2 stacked capacitor DRAM cell is realized using a quadruple-polysilicon gate structue and 0. 6 mu m pattern delineation technology. Memory operation in an experimental 4-Kbit array was successfully observed. A 5nm dielectric composite film and storage node pattern optimization by computer simulation are used to realize increased storage capacitance in this small cell. Charge retention characteristics and alpha particle immunity are favorable, indicating that this cell is a good candidate for application to 16 megabit DRAMs.

本文言語English
ホスト出版物のタイトルConference on Solid State Devices and Materials
出版社Japan Soc of Applied Physics
ページ19-22
ページ数4
ISBN(印刷版)4930813212
出版ステータスPublished - 1987

ASJC Scopus subject areas

  • 工学(全般)

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